3GPP evolved packet system (EPS) is an all-IP based system that supports various access networks such as LTE, HSPA/HSPA+ and non-3GPP networks. Recently, the support of IP flows with packet level QoS profiles has been added to the requirements of the EPS. This paper proposes an adaptive modulation and coding (AMC) scheme that supports the QoS of such IP flows in the 3G LTE access network of the EPS. Defining the retransmission as a critical factor for QoS, the proposed scheme applies different maximum packet error probability Pmax to each packet when selecting the AMC transmission mode. In determining Pmax, the QoS constraints as well as channel condition are considered, balancing two objectives: the satisfaction of the QoS and the maximization of spectral efficiency. Simulations show that it is able to reduce both delay violation and retransmission, while improving throughput in comparison with an existing scheme.

The input impedance of an antenna fluctuates because of various usage conditions, which causes a mismatch between an internal circuit and an antenna. An automatic matching system solves this problem, then this paper presents a reconfigurable impedance tuner that has a set of fixed capacitors controlled by switching p-i-n diodes. A fast control algorithm for selecting the appropriate conditions of an impedance tuner is proposed and mounted on FPGA to demonstrate the performance.

In this letter a new structure of multifunctional frequency filter using a universal voltage conveyor (UVC) is presented. The multifunctional circuit can realize a low-pass, high-pass and band-pass filter. All types of frequency filter can be realized as inverting or non-inverting. Advantages of the proposed structure are the independent control of the quality factor at the cut-off frequency and the low output impedance of output terminals. The computer simulations and measuring of particular frequency filters are depicted.

In networked control systems, uncontrollable events may unexpectedly occur in a plant before a proper control action is applied to the plant due to communication delays. In the area of supervisory control of discrete event systems, Park and Cho [5] proposed the notion of delay-nonconflictingness for the existence of a supervisor achieving a given language specification under communication delays. In this paper, we present the algebraic properties of delay-nonconflicting languages which are necessary for solving supervisor synthesis problems under communication delays. Specifically, we show that the class of prefix-closed and delay-nonconflicting languages is closed under intersection, which leads to the existence of a unique infimal prefix-closed and delay-nonconflicting superlanguage of a given language specification.

This paper presents a closed form solution to a problem of constructing the best lower bound of a convex function under certain conditions. The function is assumed (I) bounded below by -ρ, and (II) differentiable and its derivative is Lipschitz continuous with Lipschitz constant L. To construct the lower bound, it is also assumed that we can use the values ρ and L together with the values of the function and its derivative at one specified point. By using the proposed lower bound, we derive a computationally efficient deep monotone approximation operator to the level set of the function. This operator realizes better approximation than subgradient projection which has been utilized, as a monotone approximation operator to level sets of differentiable convex functions as well as nonsmooth convex functions. Therefore, by using the proposed operator, we can improve many signal processing algorithms essentially based on the subgradient projection.

This paper studies two kinds of simple switched dynamical systems with piecewise constant characteristics. The first one is based on the single buck converter whose periodic/chaotic dynamics are analyzed precisely using the piecewise linear phase map. The second one is based on a paralleled system of the buck converters for lower voltages with higher current capabilities. Referring to the results of the single system, it is clarified that stable multi-phase synchronization is always possible by the proper use of the switching strategies and adjustment of the clock period. Presenting a simple test circuit, typical operations are confirmed experimentally.

In this letter, a new estimation filtering is proposed when a delay between signal generation and signal estimation exists. The estimation filter is developed under a maximum likelihood criterion using only the finite observations on the delay interval. The proposed estimation filter is represented in both matrix form and iterative form. It is shown that the filtered estimate has good inherent properties such as time-invariance, unbiasedness and deadbeat. Via numerical simulations, the performance of the proposed estimation filtering is evaluated by the comparison with that of the existing fixed-lag smoothing, which shows that the proposed approach could be appropriate for fast estimation of signals that vary relatively quickly. Moreover, the on-line computational complexity of the proposed estimation filter is shown to be maintained at a lower level than the existing one.

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

When contact failure occurs in a connector in a coaxial HF signal transmission line, an electromagnetic field is radiated around the line. We have measured the electromagnetic field and examined the characteristics of such radiation. The results show that the radiation is related to the contact resistance and the symmetry of the distribution of contact points at the connector. When contact resistance is low, radiation is observed at resonant frequencies related to the length of the transmission line. If a connector has axially asymmetric contact points, its radiation is higher than that when the contact points are symmetric. We show that if contact points in a connector are axially symmetrical with resistance lower than 0.25 Ω, the electromagnetic interference caused by the connector contact failure is as low as the background noise.

Short-time withstand current is one of the crucial nominal parameters in air circuit breaker. A numerical method to evaluate the short-time withstand current is proposed. Cylindrical current carrying bridge is introduced to describe the contact spot between movable and fixed contacts. Taking into account the action of ferromagnetic splitter plates, the variation of the conductor properties with temperature and the variation of contact spot radius with the electro-dynamic repulsion force, a transient finite element calculation model is developed by coupling the electromagnetic field and thermal field. The loaded short circuit current is considered as the short-time withstand current once the highest temperature is near to the melting point of the contact material. It demonstrates that the method is useful to evaluate the performance of the air circuit breaker.

To predict the thermal behavior of switchgear quickly, the Thermal Network Finite Difference Analysis method (TNFDA) is adopted in thermal analysis of AC contactor in the paper. The thermal network model is built with nodes, thermal resistors and heat generators, and it is solved using finite difference method (FDM). The main circuit and the control system are connected by thermal resistors network, which solves the problem of multi-sources interaction in the application of TNFDA. The temperature of conducting wires is calculated according to the heat transfer process and the fundamental equations of thermal conduction. It provides a method to solve the problem of boundary conditions in applying the TNFDA. The comparison between the results of TNFDA and measurements shows the feasibility and practicability of the method.

We have developed a compact double-gate metal-oxide-semiconductor field-effect transistor model for circuit simulation considering the volume inversion effect by solving the Poisson equation explicitly. It is verified that applied voltage dependence of the calculated potential values both at the surface and at the center of the silicon layer reproduce 2 dimensional device simulation results for any device structure, confirming the validity of the model for device optimization.

Lightweight single-layer slotted waveguide array antennas are fabricated using plastic materials with metal-plating. A plastic material that has good heat-radiation properties is investigated. Three types of antennas are fabricated by milling, using ABS resin, heat-radiating plastic, and aluminum alloy. In measurements, all three types of antennas are confirmed to have almost the same VSWR and gain in the 25 GHz frequency band.

The fairness solution without deteriorating the system sum-rate is a challenge under a total energy constraint. One regenerative strategy is proposed to improve the fairness for bi-directional three-node relaying, which is based on decode-and-forward technique with network coding and power optimization. In this letter, the application of network coding decreases the number of transmission phases from traditional four phases to three phases. Moreover, the proposed power optimization algorithm can be applied in practical system, which transforms max-min optimization problem to linear programming (LP) with low complexity. Numerical simulations shows this strategy enhances the minimum of unidirectional transmission rate up to 94% as compared to a four-phase bi-directional strategy, and up to 46% as compared to the three-phase bi-directional strategy with equal-power allocation.

Divisible Load Theory (DLT) is an established mathematical framework to study Divisible Load Scheduling (DLS). However, traditional DLT does not address the scheduling of results back to source (i.e., result collection), nor does it comprehensively deal with system heterogeneity. In this paper, the DLSRCHETS (DLS with Result Collection on HETerogemeous Systems) problem is addressed. The few papers to date that have dealt with DLSRCHETS, proposed simplistic LIFO (Last In, First Out) and FIFO (First In, First Out) type of schedules as solutions to DLSRCHETS. In this paper, a new polynomial time heuristic algorithm, SPORT (System Parameters based Optimized Result Transfer), is proposed as a solution to the DLSRCHETS problem. With the help of simulations, it is proved that the performance of SPORT is significantly better than existing algorithms. The other major contributions of this paper include, for the first time ever, (a) the derivation of the condition to identify the presence of idle time in a FIFO schedule for two processors, (b) the identification of the limiting condition for the optimality of FIFO and LIFO schedules for two processors, and (c) the introduction of the concept of equivalent processor in DLS for heterogeneous systems with result collection.

Broadband access network planning strategies with techno-economic calculations are important topics, when optimal broadband network deployments are considered. This paper analyzes optimal deployment combination of digital subscriber line technologies (xDSL) and fiber to the home technologies (FTTx), following different user bandwidth demand scenarios. For this reason, optimal placement of remote digital subscriber line multiplexer (RDSLAM) is examined. Furthermore, the article also discusses the economy of investments, depending on certain investment threshold and the reach of different xDSL technologies. Finally, the difference between broadband network deployment in a characteristic urban and rural area in Republic of Slovenia, in terms of required optical cable dig length per household is shown. A tree structure network model of a traditional copper access network is introduced. A dynamic programming logic, with recursion as a basis of a tree structure examination and evaluation of optimal network elements placement is used. The tree structure network model considers several real network parameters (e.g.: copper cable lengths, user coordinates, node coordinates). The main input for the optimization is a local loop distance between each user and a candidate node for RDSLAM placement. Modelling of copper access networks with a tree structure makes new extensions in planning optimization of broadband access networks. Optimization of network elements placement has direct influence on efficiency and profitability of broadband access telecommunication networks.

We propose an IP broadcasting system architecture using passive optical networks (PON) utilizing the optical broadcast links of a PON with a downstream bandwidth allocation algorithm to provide a multi-channel IP broadcasting service to home subscribers on single broadband IP network infrastructures. We introduce the design and adaptation of the optical broadcast links to effectively broadcast video contents to home subscribers. We present a performance analysis that includes the downstream bandwidth utilization efficiency of the broadcast link and the bandwidth control of the IP broadcasting and Internet data. Our analysis and simulation results show that the proposed system can provide 100 HDTV channels to every user over fiber lines. We also propose an IPTV channel selection mechanism in an ONT by selecting a broadcast stream. We developed and evaluated a prototype that can achieve a 15-msec IPTV channel selection speed.

We propose an implementation of the tapped delay line adaptive array (TDLAA) at the base station for improving the BER performance of asynchronous multi-user mobile communication over fast fading channels using multiple antennas. The data of each user at the mobile station, which applies two transmit antennas, are encoded by Space Time Block Code (STBC). The proposed scheme transmits the pilot signal and information data in alternate time slots. We derive performance criteria for designing such a scheme under the assumption that the fading is classified as fast fading. We show that the proposed scheme can suppress co-channel interference (CCI) and defeat Doppler spread effectively.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.