A new class of ternary sequence with a zero-correlation zone is introduced. The proposed sequence sets have a zero-correlation zone for both periodic and aperiodic correlation functions. The proposed sequences can be constructed from a pair of Hadamard matrices of size n0n0 and a Hadamard matrix of size n1n1. The constructed sequence set consists of n0 n1 ternary sequences, and the length of each sequence is (n1+1) for a non-negative integer m. The zero-correlation zone of the proposed sequences is |τ|≤ -1, where τ is the phase shift. The sequence member size of the proposed sequence set is equal to times that of the theoretical upper bound of the member size of a sequence set with a zero-correlation zone.

A microstrip phase shifter design that uses a reconfigurable metal pattern on the EBG ground plate is introduced. The EBG ground plate metal pattern contains a linear array of thin slots with switching devices loaded at the center. This design can vary the phase constant with minimum mismatch loss over a large frequency bandwidth. Several test ground plates without actual switching devices were used to verify the design concept.

This paper proposes an adaptive transmission scheme for MIMO systems to provide different bit error rates and transmission rates for multimedia traffic. The adaptive transmission scheme allocates antennas, rate and power jointly according to the feedback information to satisfy the diverse QoS requirements of the multimedia traffic. Furthermore, an efficient search algorithm with low complexity is proposed for practical implementation. Simulation results show that the proposed scheme improves the spectral efficiency while guaranteeing the QoS requirements of multimedia traffic. Moreover, the proposed search algorithm achieves close optimal performance with great complexity reduction.

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

In this paper, we introduce a Parallel Interference Canceller (PIC) based on a sorting method to improve the performance in the MC-DS/CDMA environment. A conventional PIC estimates and cancels out all of the MAI (Multiple Access Interference) for each user in parallel. The parallel process ensures a limited delay for the detection of all users. Since the performance of PIC is strongly related to the correct MAI estimation, we introduce an interference cancellation scheme to estimate accurately the MAI of the weaker interferers than the desired signal. The principle of proposed IC (Interference cancellation) scheme is to sort in descending order from the strength of the signal and subtracted by the MAI of the strong interferer from the weak signal. Therefore, the signal of the weak interferer becomes a better estimation. Following this, the output of the front processing is achieved by a rank operation of the signals in an ascending order of strength. Then the strong signal eliminates the improved weak interferer. Resulting from this, the proposed scheme obtains a better BER performance than the conventional PIC, because the accuracy of the strong signal has been improved. However, a disadvantage exists in that the processing time has a slightly longer delay than the PIC-1stage owing to a two step processing, including the sorting one.

Recent work has shown that the usage of multiple antennas at the transmitter and receiver in a flat fading environment results in a linear increase in channel capacity. But increasing the number of antennas induces the higher hardware costs and computational burden. To overcome those problems, it is effective to select antennas appropriately among all available ones. In this paper, a new antenna selection method is proposed. The transmit antennas are selected so as to maximize the channel capacity using the genetic algorithm (GA) which is the one of the general random search algorithm. The results show that the proposed GA achieves almost the same performance as the optimal selection method with less computational amount.

The latest processors employ a large instruction window and longer pipelines to achieve higher performance. Although current branch predictors show high accuracy, the misprediction penalty is getting larger in proportion to the number of pipeline stages and pipeline width. This negative effect also happens in case of exceptions or interrupts. Therefore, it is important to recover processor state quickly and restart processing immediately. In this letter, we propose a low-cost recovery mechanism for processors with large instruction windows.

Recently, Yoon et al. exhibited the vulnerability of the smart-card-equipped password based authentication protocol proposed by Chien et al. to the Denning-Sacco attack. Furthermore, they also pointed out that the protocol does not provide the perfect forward secrecy. Accordingly, they presented an enhanced protocol to strengthen the security. This letter, however, demonstrates an interleaving attack on the Yoon et al.'s improved protocol and also discusses how to defend the protocol from the attack presented here.

In this paper, we propose an interactive instruction system named IMPRESSION, which allows performance of interactive presentations using multimedia educational materials in class. In recent years, although many practices of educational methodology with information technology and presentation tools using multimedia resources as educational materials have come into common use, instructors can only present such materials in a slide-sheet form through the use of such presentation tools in class. Therefore, instructors can neither do formative evaluations nor can they present suitable materials according to students' reactions in class. Our proposed methodology employs a scenario-based approach in a double loop instructional design process to overcome such problems. Instructors design an instructional plan as a scenario, and subsequently implement and modify the plan through formative evaluation during the class. They then conduct a summative evaluation based on planned and implemented instructions for redesign. To realize our methodology, in this paper we propose and design an instruction system that provides functions to select and present multimedia materials interactively provided on the Internet during the class; we then record these instructions. After implementing it, we confirmed that we can conduct the class flexibly based on our methodology through its practical use in an actual classroom environment.

According to the Gestalt principals, this paper presents a recognition method of grouping areas in trademark images modeling features for measuring the attraction degree between couples of image components. This investigation would be used for content-based image retrieval from the view of mirroring human perception for images. Depending on variability in human perception for trademark images, the proposed method finds grouping areas by calculating Mahalanobis distance with the features to every combination of two components in images. The features are extracted from every combination of two components in images, and the features represent proximity, shape similarity, and closure between two components. In addition, changing combination of the features, plural grouping patterns are output. Besides, this paper shows the efficiency and limits of the proposed method from experimental results. In the experiments, 104 participants have perceived grouping patterns to 74 trademark images and the human perceptions have been compared with outputs by the proposed method for the 74 images.

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.

A new simply implemented collusion-attack free identity-based non-interactive key sharing scheme (ID-NIKS) has been proposed. A common-key can be shared by executing only once a modular exponentiation which is equivalent to RSA deciphering, and the security depends on the difficulty of factoring and the discrete logarithm problem. Each user's secret information can be generated by solving two simple discrete logarithm problems and synthsizing their solutions by linear combination. The detail comparison with the Maurer-Yacobi's scheme including its modified versions shows that the computational complexity to generate each user's secret information is much smaller and the freedom to select system parameters is much greater than that of the Maurer-Yacobi's scheme. Then our proposed scheme can be implemented very easily and hence it is suitable for practical use.

This paper proposes a simple and efficient method to numerically obtain the mapping degree deg(f, 0, B) of a C1 map f : Rn → Rn at a regular value 0 relative to a bounded open subset B ⊂ Rn. For practical application, this method adopts Aberth's algorithm which does not require computation of derivatives and determinants, and reduces the computational cost with two additional procedures, namely preconditioning using the coordinate transformation and pruning using Krawczyk's method. Numerical examples show that the proposed method gives the mapping degree with 2n+1 operations using interval arithmetic.

This paper describes an efficient PCRD (Post-Compression Rate-Distortion) scheme for rate control of JPEG2000. The proposed method determines the rate constant in consideration of the decreasing characteristic of RD-slopes and conducts rate allocation about only coding passes excluded from the previous rate allocation. As a result, it can considerably reduce the number of operations and encoding time with nearly the same PSNR performance as the conventional rate control scheme of JPEG2000.

This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.

A hardware algorithm for computing the reciprocal of the Euclidean norm of a 3-dimensional (3-D) vector which appears frequently in 3-D computer graphics is proposed. It is based on a digit-recurrence algorithm for computing the Euclidean norm and an on-line division (on-line reciprocal computation) algorithm. These algorithms are modified, so that the reciprocal of the Euclidean norm is computed by performing on-line division where the divisor is the partial result of Euclidean norm computation. Division, square-rooting, and reciprocal square-root computation, which are important operations in 3-D graphics, can also be performed using a circuit based on the proposed algorithm.

An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

Electrical capacitance tomography (ECT) is used to obtain information about the distribution of a mixture of dielectric materials inside a vessel or pipe. ECT has several advantages over other reconstruction algorithms and has found many applications in the industrial fields. However, there are some difficulties with image reconstruction in ECT: The relationship between the permittivity distribution and measured capacitance is nonlinear. And inverse problem is ill-posed so that the inverse solution is sensitive to measurement error. To cope with these difficulties iterative image reconstruction algorithms have been developed. In general, the iterative reconstruction algorithms in ECT have comparatively good-quality in reconstructed images but result in intensive computational burden. This paper presents the iterative image reconstruction algorithm for ECT that can enhance the speed of image reconstruction without degradation in the quality of reconstructed image. The main contribution of the proposed algorithm is new weighting matrices, which are obtained by the interpolation of the grouped electrical field centre lines (EFCLs). Extensive simulation results have demonstrated that proposed algorithm provides improved reconstruction performance in terms of computational time and image quality.

The path coloring problem is to assign the minimum number of colors to a given set P of directed paths on a given symmetric digraph D so that no two paths sharing an arc have the same color. The problem has applications to efficient assignment of wavelengths to communications on WDM optical networks. In this paper, we show that the path coloring problem is NP-hard even if the underlying graph of D is restricted to a binary caterpillar. Moreover, we give a polynomial time algorithm which constructs, given a binary caterpillar G and a set P of directed paths on the symmetric digraph associated with G, a path coloring of P with at most colors, where L is the maximum number of paths sharing an edge. Furthermore, we show that no local greedy path coloring algorithm on caterpillars in general uses less than colors.