The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.

The network duplicating can achieve significant improvements of the Local Area Network (LAN)'s performance, availability, and security. For LAN duplicating, a Dual-Path Ethernet Module (DPEM) is developed. Since a DPEM is simply located at the front end of any network device as a transparent add-on type independent hardware machine, it does not require sophisticated server reconfiguration. We examine the desirable properties and the characteristics on the Dual-LAN structure. Our evaluation results show that the developed scheme is more efficient than the conventional Single-LAN structures in various aspects.

This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

This paper investigates an accurate channel estimation method using the common pilot channel (CPICH) in addition to a dedicated pilot channel (PICH) when the fading correlation between the dedicated PICH and CPICH is high, and clarifies the area in which the proposed channel estimation method is effective for adaptive antenna array transmit diversity (AAA-TD) in the forward link. Computer simulation results elucidate that although a more precise channel estimation is possible by using the primary-CPICH (P-CPICH) transmitted from an omni-directional antenna in addition to the dedicated PICH for the area where the distance, d, between a base station and a mobile terminal is longer than approximately 200 m, no improvement is obtained for the area where the value of d is shorter than approximately 200 m. Meanwhile, by employing the secondary-CPICH (S-CPICH) transmitted with several directional beams in addition to the dedicated PICH, the required average received Eb/N0 at the average BER of 10-3 is decreased by approximately 0.4 (0.2-0.4) dB compared to the channel estimation method using only the dedicated PICH regardless of the value of d when the number of antennas is 4 (8).

In this paper, a new approach is proposed to improve the channel estimation accuracy with channel tracking capability for adaptive multicarrier equalization systems under time-variant multipath fading channel. The improvement is carried out based on the assumption that the channel is static over a transmitted block period, and slowly linearly changing over several block periods. By applying IFFT to the concatenated channel transfer function derived from different blocks, the noise-averaging improvement is achieved, and a better estimation of the channel coefficients with some delay can be obtained. A multi-step channel predictor and a smoothing filter is utilized to compensate for the delay and make the system more robust in terms of channel tracking performance. Adaptive time domain equalization is jointly performed with this approach to avoid the channel invertibility problem found in the frequency domain approach. A short period of training sequences is utilized resulting in more efficient use of available communication capacity. The effectiveness of the proposed approach is evaluated through simulation for multicarrier systems in time-variant multipath fading channels. Results show improvement over previous channel estimation schemes.

When we use an adaptive array antenna (AAA) with the minimum mean square error (MMSE) criterion under the multipath environment, where the receiving signal level varies, it is difficult for the AAA to converge because of the distortion of the desired wave. Then, we need the equalization both in space and time domains. A tapped-delay-line adaptive array antenna (TDL-AAA) and the AAA with linear equalizer (AAA-LE) have been proposed as simple space-temporal equalization. The AAA-LE has not utilized the recursive least square (RLS) algorithm. In this paper, we propose a space-temporal simultaneous processing equalizer (ST-SPE) that is an AAA-LE with the RLS algorithm. We proposed that the first tap weight of the LE should be fixed and the necessity of that is derived from a normal equation in the MMSE criterion. We achieved the space-temporal simultaneous equalization with the RLS algorithm by this configuration. The ST-SPE can reduce the computational complexity of the space-temporal joint equalization in comparison to the TDL-AAA, when the ST-SPE has almost the same performance as the TDL-AAA in multipath environment with minimum phase condition such as appeared at line-of-sight (LOS).

The modern network service of finding the optimal path subject to multiple constraints on performance metrics such as delay, jitter, loss probability, etc. gives rise to the multi-constrained optimal-path (MCOP) QoS routing problem, which is NP-complete. In this paper, this problem is solved through both exact and heuristic algorithms. We propose an exact algorithm E_MCOP, which first constructs an aggregate weight and then uses a K-shortest-path algorithm to find the optimal solution. By means of E_MCOP, the performance of the heuristic algorithm H_MCOP proposed by Korkmaz et al. in a recent work is evaluated. H_MCOP only runs Dijkstra's algorithm (with slight modifications) twice, but it can find feasible paths with a success ratio very close to that of the exact algorithm. However, we notice that in certain cases its feasible solution has an unsatisfactorily high average cost deviation from the corresponding optimal solution. For this reason, we propose some modified algorithms based on H_MCOP that can significantly improve the performance by running Dijkstra's algorithm a few more times. The performance of the exact algorithm and heuristics is investigated through computer simulations on networks of various sizes.

A software defined radio (SDR) prototype based on a multiprocessor architecture (MPA) is developed. Software for Japanese personal handy phone system (PHS) of a 2G mobile system, and IEEE 802.11 wireless LAN, which has much wider bandwidth than the 2G systems, is successfully implemented. Newly developed flexible-rate pre-/ post-processor (FR-PPP) achieves the flexibility and wideband performance that the platform needs. This paper shows the design of the SDR prototype and evaluates its performance by experiments that include PHS processor load and wireless LAN throughput characteristics and processor load.

In this paper, a digital compensation scheme for coefficient errors of a complex filter bank parallel A/D converter in low-IF receivers is presented. The complex filter bank is employed to suppress DC offset and image signals in the low-IF receivers and relax the requirements on the conversion rate and resolution of A/D converters. The proposed compensation scheme regenerates interference due to coefficient errors and subtracts it from the digital signal converted by an A/D converter. The proposed scheme also improves the effective resolution of A/D converters.

Computing the Eigen Value Decomposition (EVD) of a symmetric matrix is a frequently encountered problem in adaptive (or smart or software) antenna signal processing, for example, super resolution DOA (Direction Of Arrival) estimation algorithms such as MUSIC (MUltiple SIgnal Classification) and ESPRIT (Estimation of Signal Parameters via Rotational Invariance Technique). In this paper the hardware architecture of the fast EVD processor of symmetric correlation matrices for the application of an adaptive antenna technology such as DOA estimation is proposed and the basic idea is also presented. Cyclic Jacobi method is well known for the simplest algorithm and easily implemented but its convergence time is slower than other factorization algorithm like QR-method. But if considering the fast parallel computation of the EVD with a hardware architecture like ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), the Jacobi method can be a appropriate solution, since it offers a quite higher degree of parallelism and easier implementation than other factorization algorithms. This paper computes the EVD using a Jacobi-type method, where the vector rotations and the angles of the rotations are obtained by CORDIC (COordinate Rotation DIgital Computer). The hardware architecture suitable for ASIC or FPGA with fixed-point arithmetic is presented. Because it consists of only shift and add operations, this hardware friendly feature provides easy and efficient implementation. In this paper, the computational load, the estimate of circuit scale and expected performance are discussed and the validation of fixed-point arithmetic for the practical application to MUSIC DOA estimation is examined.

Asymmetric networks, which provide asymmetric bandwidth or delay for upstream and downstream transfer, have recently gained much attention since they support popular applications such as the World Wide Web (WWW). HTTP (Hypertext Transfer Protocol) is the basis of most WWW services so, evaluating the performance of HTTP on asymmetric networks is increasingly important, particularly real-world networks. However, the performance of HTTP on the asymmetric networks composed of satellite and terrestrial links has not sufficiently evaluated. This paper proposes new formulas to evaluate the performance of both HTTP1.0 and HTTP1.1 on asymmetric networks. Using these formulas, we calculate the time taken to transfer web data by HTTP1.0/1.1. The calculation results are compared to the results of an existing theoretical formula and experimental results gained from a system that combines a VSAT (Very Small Aperture Terminal) satellite communication system for satellite links (downstream) and the Internet for terrestrial links (upstream). The comparison shows that the proposed formulas yield more accurate results (compared to the measured values) than the existing formula. Furthermore, this paper proposes an evaluation formula for pipelined HTTP1.1, and shows that the values output by the proposed formula agree with those obtained by experiments (on the VSAT system) and simulations.

The off-state shunt GaAs FET, which is the most important for low distortion operation of the high power RF switch IC, is a very complicated device to analyze the RF voltage. Because the conventional measurement method has an influence on the behavior of the switch, it has not provided the correct measurement value. In this paper, we have realized a measurement method without touching the surface of the switch IC using EO-probe. As a result we achieved extremely low second and third harmonics of 70.5 dBc and 75.2 dBc, respectively at the input power of 35 dBm by adoptin SPDT switch IC composed of the multi-gate FET for the thru FET and the stacked-gate FET.

This paper presents the theoretical analysis of subband adaptive array combining cyclic prefix transmission scheme (SBAA-CP) in multipath fading environment. The exact expressions for optimal weights, array outputs and the output signal to interference plus noise ratio (SINR) are derived. The analysis shows that use of the cyclic prefix data transmission scheme can significantly improve the performance of subband adaptive array (SBAA). An example of implementing SBAA-CP as a software antenna is also presented.

We present the effects of N2O plasma treatment for hot carrier reliability and gate oxide stability in excimer-laser annealed poly-Si TFTs. N2O plasma treatment between SiO2 and poly-Si suppresses both the reduction in mobility caused by hot carrier stress and the Vth shift caused by gate bias stress. The results of XPS spectra and the energy distribution of the trap state density of stressed TFTs show that the introduction of Si-N bonds plays an important role in poly-Si TFT reliability.

In this paper, three algorithms are proposed for rate maximization (RM) of transmitted data in multichannel (MC) communications, subject to joint constraints on available energy budget and tolerable degradation of service (DOS). Altogether referred to as the RM algorithms, they consist of the EADRM, the DADRM, and the fDADRM algorithms. Based on the rate-distortion optimization theory, closed-form expressions for optimally distributing the energy (for EADRM) or DOS (for DADRM and fDADRM ) among the subchannels (SC's) are derived, when the bit allocation is pre-specified. The specification of bit allocations is achieved by the use of the so-called eligible bit allocation matrix (EBAM), which is a function of the total data rate and the number of SC's. A greedy approach is adopted, where the total data rate is kept on raising until the relevant constraints can no longer be satisfied. While all three RM algorithms essentially generate identical maximum data rates, the fDADRM algorithm is much faster than the other two in computation. As compared to the result achievable by a single-channel communication scheme, the RM algorithms produce a much higher data rate for spectrally shaped channels.

Model checking is a technique that can make a verification for finite state systems absolutely automatic. We propose a method for automatic verification of fault-tolerant concurrent systems using this technique. Unlike other related work, which is tailored to specific systems, we are aimed at providing an approach that can be used to verify various kinds of systems against fault tolerance. The main obstacle in model checking is state explosion. To avoid the problem, we design this method so that it can use a symbolic model checking tool called SMV (Symbolic Model Verifier). Symbolic model checking can overcome the problem by expressing the state space and the transition relation by Boolean functions. Assuming that a system to be verified is modeled as a guarded command program, we design a modeling language and propose a translation method from the modeling language to the input language of SMV. We show the results of applying the proposed method to various examples to demonstrate the feasibility of the method.

This paper presents circuit models for the description of the frequency-dependent behavior of coils for horizontal deflection in CRTs. This enables CRT circuit designers to use circuit simulation programs to predict the high-frequency behavior of the interaction between the deflection coils and the drive circuit. An overview is given of the major phenomena that occur in CRT deflection coils at various frequencies. Models are presented for the dissipative, the capacitive, and the resonant behavior in successive frequency intervals. With these models, phenomena such as power dissipation and ringing can not only be related to design parameters, but can also be calculated from impedance characteristics which are relatively easy to measure.

In this paper, we consider a flexible method for designing n-entities communication protocols and services. The proposed technique considers alternative and parallel composition of n service specifications and n protocol specifications, where n 2. The specifications are specified in Basic LOTOS which is a Formal Description Technique (FDT). We use the weak bisimulation equivalence () to represent the correctness properties between the service specification and the protocol specification.

The fields in the junctions between straight and curved rectangular waveguides are analyzed by using the method of separating variables. This method was succeeded because the authors developed the method of numerical calculation of the cylindrical functions of complex order. As a result, we numerically calculate the reflection and transmission coefficients in the junctions in various situations, and we compare these results with the results by the perturbation method and with the results by Jui-Pang et al.

Performance evaluation criterion is one of the most important issues for design of network traffic control mechanisms and algorithms. Due to multiple performance objectives of network traffic control, performance evaluation criteria must include multiple performance metrics executed simultaneously, which is called integrated performance evaluation criteria. In this paper, we analyze various performance metrics of network traffic control, and propose three integrated performance evaluation criteria. One is the improvement on original Power formula; our new Power formula is based on the multi-service-class model. Another is about the fairness of user's QoS (Quality of Service) requirements (queuing delay and loss rate); especially the detailed discussion on Proportional Fairness Principle is given. And the third one is the integration of preceding two, in which the throughput, queuing delay, packet loss rate, and the fairness are considered simultaneously.