The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.

This paper presents an efficient Hybrid Learning Algorithm (HLA) for Radial Basis Function Neural Network (RBFNN). The HLA combines the gradient method and the linear least squared method for adjusting the RBF parameters and connection weights. The number of hidden neurons and their characteristics are determined using an unsupervised clustering procedure, and are used as input parameters to the learning algorithm. We demonstrate that the HLA, while providing faster convergence in training phase, is also less sensitive to training and testing patterns. The proposed HLA in conjunction with RBFNN is used as a classifier in a face recognition system to show the usefulness of the learning algorithm. The inputs to the RBFNN are the feature vectors obtained by combining shape information and Pseudo Zernike Moment (PZM). Simulation results on the Olivetti Research Laboratory (ORL) database and comparison with other algorithms indicate that the HLA yields excellent recognition rate with less hidden neurons in human face recognition.

This study investigates the anisotropy substrate and dielectric cover effects of the rectangular microstrip patch antenna on anisotropy substrates with air gap, based on rigorous full-wave analysis and Galerkin's moment method. Results show that the resonant frequencies in the variation of air gap, patch length, and permittivity of superstrate can be determined and analyzed with varying dielectric cover thickness.

This paper presents a framework for modeling and mixed-mode simulation of circuits/interconnects and electromagnetic (EM-) radiations. The proposed framework investigates the signal integrity in VLSI chips, packages and wiring boards at the GHz-band level, and verifies the electromagnetic interference (EMI) and the electromagnetic compatibility (EMC) of high-speed systems. In our framework, the frequency characteristics of interconnects and EM-radiations are extracted by the full-wave FDTD simulation. The macromodels of interconnects are synthesized as SPICE subcircuits, and the impulse responses of EM-radiations are stored in the database. Once the macromodels are synthesized, the circuit simulation with the consideration of EM-effects can be performed by using SPICE. The EM-field distributions can be also easily calculated by taking convolutions of pre-simulated EM impulse responses and the SPICE results.

As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.

For an uncertain discrete event system (DES) modeled as a set of some possible nondeterministic automata, we address robust supervisory control problems. Based on language models, this paper presents the existence conditions of a robust nonblocking (RN) supervisor that guarantees the absence of blocked states in a closed-loop system. We show that an RN supervisor achieves both a given language specification and the nonblocking characteristics of any nondeterministic automata of the set.

A term rewriting system which effectively preserves recognizability (EPR-TRS) has good mathematical properties. In this paper, a new subclass of TRSs, layered transducing TRSs (LT-TRSs) is defined and its recognizability preserving property is discussed. The class of LT-TRSs contains some EPR-TRSs, e.g., {f(x)f(g(x))} which do not belong to any of the known decidable subclasses of EPR-TRSs. Bottom-up linear tree transducer, which is a well-known computation model in the tree language theory, is a special case of LT-TRS. We present a sufficient condition for an LT-TRS to be an EPR-TRS. Also reachability and joinability are shown to be decidable for LT-TRSs.

This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.

TCP congestion control is receiving increased attention in recent years due to their usefulness for network stability, robustness use of network buffer and bandwidth resources on an end-to-end per-connection basis. The RED scheme was designed for a network where a single dropped packet is sufficient to signal the presence of congestion to the TCP protocol. This paper applies matrix-analytic approach to analyze both the long-term and the short-term drop behaviors of a queue with RED scheme and uses this model to quantify the benefits brought about by RED. The result shows that the drop probability between RED and Drop-Tail is very close under heavy load conditions. This indicates that RED not only can resolve the synchronization problem but also has the same loss performance with Drop-Tail scheme under the heavy load circumstances. Our findings also show that the rate oscillation behavior of RED is better than Drop-Tail when TCP applies the additive-increase and multiplication-decrease mechanism. As a consequence, it can help reduce the required buffer capacity in the RED router.

In the past, enhancement techniques for the end-to-end quality of a networked application were studied by looking at each individual layer. Examples of such techniques include the error resilience/concealment methods in the application layer, the FEC/ARQ in the transport layer, and the Quality of Service (QoS) techniques in the network layers. However, an integrated approach that would look across all related layers had yet to be investigated. This paper proposes an approach that combines priority-aware video packetization, adaptively used layered FEC, and QoS controlled networks such as IntServ and DiffServ in order to provide an efficient end-to-end quality in layered streaming video. The combination is more efficient in terms of a simple network price mechanism, that is, in getting the best end-to-end quality under a given total cost constraint. Our proposed approach in DiffServ with video packet (VP) data-splitting and layered FEC guarantees minimal service quality in a scalable and cost effective manner without introducing resource reservation. For video, we also propose performance metrics such as corrupted/frozen frame ratio (CFR, FFR). These provide objective metrics like PSNR as well as a measurement for subjective perceptions. Our approach, which combines related layers such as video coding, transport, and network, has yielded results that have proven to be more cost-effective and practical than the supporting network QoS.

The ATM-ABR service category provides minimum cell rate (MCR) guarantees and robust connections even with insufficient network resources. Recently proposed rate-management algorithms for supporting multimedia applications over ABR mainly aim at minimizing the cell loss and delay. However, jitter is also an important element of QoS for multimedia applications. In this paper, we focus our attention on the arrival point of the critical cell corresponding to the end of data packet and propose a simple cell scheduling scheme for source node to reduce the jitter on application level over the ATM-ABR service class. In our proposed method, critical cells are delayed intentionally and the packet stream at application level becomes smooth. We verify the effectiveness of our proposed algorithm by an analytical model and simulation. From those results, we find that our proposed scheduling algorithm is effective in reducing the application level jitter even when the tagged cell stream is transmitted along the path with multiple nodes.

A novel ultra-broad-band bridge-type switch is proposed, which employs a bridge circuit consisting of four common-gate FETs. The isolation of conventional series- and shunt-type switches is limited by the switching device's performance, namely, the ON resistance (Ron) and the OFF capacitance (Coff). Some methods have been proposed to overcome this problem. However, most of them are band-limited. A feature of the newly-developed bridge-type switch is that its isolation characteristics do not depend on the Ron and Coff of the switching devices, but instead on the accuracy of the balancing bridge circuit, and thus ultra-broad-band characteristics can be obtained. The isolation for deviation of the bridge circuit elements and ON-state characteristics are calculated using a simple FET model. The fabricated bridge-type MMIC switch achieves less than 3.0 dB insertion loss and greater than 28 dB isolation in the broad frequency band up to 40 GHz.

Basic characteristics of a short-ended half-wavelength resonator made of a coplanar waveguide (CPW) and their applications to bandpass filters (BPFs) are discussed. The first part of this paper gives the essence for improving out-of-band characteristics of the BPF by describing the basic characteristics of a tap-coupled resonator. Secondly, a new BPF with attenuation poles using the short-ended half-wavelength CPW resonators is proposed and realized. It is confirmed that our methodology is useful for improving out-of-band characteristics of the BPF using the short-ended half-wavelength CPW resonators without complicated filter design.

This paper presents a practical implementation scheme of the variable gain amplifier (VGA) using a Cds photo coupler (Cds PC) as a variable resister at the feedback loop. The fundamental design policies of IF amplifier stage in superheterodyne receiver were described. We demonstrated the VGA's experimental results. The results indicated the excellent IIP3 of +25 dBm achieved by a gain of 15 dB, and the reasonable thermal stability and variable gain range. Third-order intermodulation distortion (IMD3) comparison between the proposed VGA and conventional PIN diode attenuation type VGA was evaluated and the result indicated that the proposed VGA surpassed the PIN VGA. The proposed VGA was practically fabricated in 455 kHz IF amplifier stage for an airborne VHF communication receiver in order to improve the large signal handling capability to eliminate numerous interferences resulting from the collocated airborne VHF communication systems on the aircraft.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce Electro-Magnetic Interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudo-random dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can significantly reduce noise power spectrum peaks at the DC-DC converter output. For our test case circuit, measurements showed that noise power was reduced by 5.7 dBm at the main peak, by 15.6 dBm at the second peak and by 12.8 dBm at the third peak. This simple, inexpensive technique can be applied to most conventional switching regulators by adding simple digital circuitry, and without any modification of the design of other parts.

We propose herein a motion detection artificial vision model which uses analog electronic circuits. The proposed model is comprised of four layers. The first layer is a differentiation circuit of the large CR coefficient, and the second layer is a differentiation circuit of the small CR coefficient. Thus, the speed of the movement object is detected. The third layer is a difference circuit for detecting the movement direction, and the fourth layer is a multiple circuit for detecting pure motion output. When the object moves from left to right the model outputs a positive signal, and when the object moves from right to left the model outputs a negative signal. We first designed a one-dimensional model, which we later enhanced to obtain a two-dimensional model. The model was shown to be capable of detecting a movement object in the image. Using analog electronic circuits, the number of connections decrease and real-time processing becomes feasible. In addition, the proposed model offers excellent fault tolerance. Moreover, the proposed model can be used to detect two or more objects, which is advantageous for detection in an environment in which several objects are moving in multiple directions simultaneously. Thus, the proposed model allows practical, cheap movement sensors to be realized for applications such as the measurement of road traffic volume or counting the number of pedestrians in an area. From a technological viewpoint, the proposed model facilitates clarification of the mechanism of the biomedical vision system, which should enable design and simulation by an analog electric circuit for detecting the movement and speed of objects.

A dual-polarized multimode CDMA based local multipoint distribution system (LMDS) is presented. The twisted sector concept and narrowed sector cell are proposed to improve the system performance. Inter-cell interference is analyzed and discussed for the downstream direction based on hexagonal cell architecture. The bit error rate (BER) performance of a multimode CDMA scheme is investigated in terms of the worst case for high order modulation. The simulation results show that the proposed cell structure obtains better power efficiency and makes the multimode CDMA scheme feasible in LMDS deployment.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

This paper presents a miniaturized reverse-phase hybrid ring by the use of shunt capacitors, and successfully designs a very miniature hybrid ring of a 0.28-wavelength circumference with a wide bandwidth comparable to the regular reverse-phase hybrid ring based on the equivalent admittance approach. Moreover, a method of broadening the bandwidth with adding a matching network consisting of a very short transmission line and two shunt capacitors at each port is also described. The validity of the proposed design is demonstrated by electromagnetic simulator (Sonnet em) for a uniplanar hybrid ring.