In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing 2.3 V under 2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits.

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

In this paper, an associative memory model with a forgetting process proposed by Mezard et al. is investigated as a means of storing sparsely encoded patterns by the SCSNA proposed by Shiino and Fukai. Similar to the case of storing non-sparse (non-biased) patterns as analyzed by Mezard et al., this sparsely encoded associative memory model is also free from a catastrophic deterioration of the memory caused by memory pattern overloading. We theoretically obtain a relationship between the storage capacity and the forgetting rate, and find that there is an optimal forgetting rate leading to the maximum storage capacity. We call this the optimal storage capacity rate. As the memory pattern firing rate decreases, the optimal storage capacity increases and the optimal forgetting rate decreases. Furthermore, we shown that the capacity rate (i.e. the ratio of the storage capacity for the conventional correlation learning rule to the optimal storage capacity) is almost constant with respect to the memory pattern firing rate.

In this letter, we address geometry coding of 3-D mesh models. Using a joint prediction, the encoder predicts vertex positions in the layer traversal order. After we apply the joint prediction algorithm to eliminate redundancy among vertex positions using both position and angle values of neighboring triangles, we encode those prediction errors using a uniform quantizer and an entropy coder. The proposed scheme demonstrates improved coding efficiency for various VRML test data.

In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.21.2 mm2. The power dissipation of the chip is about 0.4 W at the clock rate of 80 MHz.

Recursive least absolute(RLA) error algorithm is derived which is basically the sign algorithm (SA) combined with recursive estimation of the inverse covariance matrix of the reference input. The name RLA comes from the absolute error criterion. Analysis of the transient behavior and steady-state performance of the RLA algorithm is fully developed. Results of experiment show that the RLA algorithm considerably improves the convergence rate of the SA while preserving the robustness against impulse noise. Good agreement between the simulation and the theoretically calculated convergence validates the analysis.

Harmonic distortions of a recently developed lightweight film-type ESPAR (Electronically Steerable Passive Array Radiator) antenna are investigated experimentally. These distortions arise from the nonlinearity of the varactor diodes that are directly integrated with the parasitic radiator elements to control the antenna's radiation pattern. A reactive-near-field measurement technique that employs low-interference probes in an ultra-small anechoic box is used to reduce experimental time and cost. An anti-series varactor pair is introduced and compared with the conventional single varactor. Consequently, an ESPAR antenna equipped with the anti-series varactor pair exhibits remarkable suppression of nonlinear distortion. In particular, the second- and the third-order harmonic is reduced by approximately 20 dB and 12 dB from the level of a single varactor type ESPAR antenna, respectively.

Near-fields of electromagnetic waves scattered by slightly rough metal surfaces which support the surface plasmon mode at optical frequencies were studied theoretically by using the stochastic functional approach. Fidelity of near-field intensity images, defined by the correlation coefficient between the surface profile and the intensity of the scattered wave field, was investigated in order to discuss field distributions of the surface plasmon on complicated structures. We show that the fidelity strongly depends on the incident wavenumber and polarization when the incident wave corresponds to the surface plasmon mode.

This paper presents the theoretical analysis of subband adaptive array combining cyclic prefix transmission scheme (SBAA-CP) in multipath fading environment. The exact expressions for optimal weights, array outputs and the output signal to interference plus noise ratio (SINR) are derived. The analysis shows that use of the cyclic prefix data transmission scheme can significantly improve the performance of subband adaptive array (SBAA). An example of implementing SBAA-CP as a software antenna is also presented.

16-bit Asian language codes can not be compressed well by conventional 8-bit sampling text compression schemes. Previously, we reported the application of a word-based text compression method that uses 16-bit sampling for the compression of Japanese texts. This paper describes our further efforts in applying a word-based method with a static canonical Huffman encoder to both Japanese and Chinese texts. The method was proposed to support a multilingual environment, as we replaced the word-dictionary and the canonical Huffman code table for the respective language appropriately. A computer simulation showed that this method is effective for both languages. The obtained compression ratio was a little less than 0.5 without regarding the Markov context, and around 0.4 when accounting for the first order Markov context.

The off-state shunt GaAs FET, which is the most important for low distortion operation of the high power RF switch IC, is a very complicated device to analyze the RF voltage. Because the conventional measurement method has an influence on the behavior of the switch, it has not provided the correct measurement value. In this paper, we have realized a measurement method without touching the surface of the switch IC using EO-probe. As a result we achieved extremely low second and third harmonics of 70.5 dBc and 75.2 dBc, respectively at the input power of 35 dBm by adoptin SPDT switch IC composed of the multi-gate FET for the thru FET and the stacked-gate FET.

We suggest a new probe message structure and an efficient probe-based deadlock detection and recovery algorithm that can be used in distributed database systems. We determine the characteristics of the probe messages and suggest an algorithm that can reduce the communication cost required for deadlock detection and recovery.

A receiver structure, which has linear computational complexity with the number of users, is proposed for decoding multiuser information data in a convolutionally coded asynchronous DS-CDMA system in multipath fading channels. The proposed receiver architecture consists of a multiuser likelihood calculator followed by a bank of soft-input soft-output (SISO) channel decoders. Information is fed back from SISO channel decoders to multiuser likelihood calculator, and the processing proceeds in an iterative fashion analogous to the decoding of turbo codes. A simplification to the above receiver structure is given too. Simulation results demonstrate that for both receiver structures at high signal-to-noise ratios (SNR) both multiple-access interference (MAI) and inter-symbol interference (ISI) are efficiently suppressed, and single-user performance is approached. Furthermore, the proposed iterative receiver is near-far resistant.

Parallelization of the P-complete problem is known to be difficult. In this paper, we consider the parallelizability of a stack breadth-first search (stack BFS) problem, which is proved to be P-complete. We first propose the longest path length (LPL) as a measure for the P-completeness of the stack BFS. Next, using this measure, we propose an efficient parallel algorithm for the stack BFS. Assuming the size and LPL of an input graph are n and l, respectively, the complexity of the algorithm indicates that the stack BFS is in the class NCk+1 if l = O(logk n), where k is a positive integer. In addition, the algorithm is cost optimal if l=O(nε), where 0 < ε < 1.

In this paper, we propose and describe a new synchronizer for the FFT timing applicable to multi-carrier spread-spectrum (MC-SS) communication systems. The performance of the synchronizer is evaluated in terms of false- and miss-detection probabilities in the presence of additive white Gaussian noise (AWGN) and Rayleigh fading.

Distributed Denial of Service (DDoS) attacks are a pressing problem on the Internet as demonstrated by recent attacks on major e-commerce servers and ISPs. Since the attack is highly distributed, an effective solution must be formulated with a distributed approach. Recently, some solutions, in which intermediate network nodes filter or shape congested traffic, have been proposed. These solutions may decrease the congested traffic, but they still cause "collateral victims problem," that is, legitimate packets may be discarded mistakenly. In this paper, we propose Active Countermeasure Platform to minimize traffic congestion and to address the collateral victim problem using the Active Networks paradigm, which incorporates programmability into intermediate network nodes. Our platform can prevent overloading of the target and consuming the network bandwidth of both the backbone and the protected site autonomously. In addition, it can improve the collateral victim problem based on user policy. This paper shows the concept of our platform, system design and evaluation of the effectiveness using a prototype.

This paper presents a rough sets-based method for clustering nominal and numerical data. This clustering result is independent of a sequence of handling object because this method lies its basis on a concept of classification of objects. This method defines knowledge as sets that contain similar or dissimilar objects to every object. A number of knowledge are defined for a data set. Combining similar knowledge yields a new set of knowledge as a clustering result. Cluster validity selects the best result from various sets of combined knowledge. In experiments, this method was applied to nominal databases and numerical databases. The results showed that this method could produce good clustering results for both types of data. Moreover, ambiguity of a boundary of clusters is defined using roughness of the clustering result.

The optimization of path bandwidth allocation in large-scale telecommunication networks is studied. By introducing a decomposition-coordination scheme to global optimization of the path bandwidth allocation which aims at minimizing the worst case call blocking probabilities in the network, the spatial and time complexities are both reduced, while the accuracy is almost the same as that given by direct optimization.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.