This paper presents a new method to evaluate time stamping schemes from three viewpoints: integrity of a time stamp, cost of issuing and verifying a time stamp and availability of the schemes. The main advantage of the proposed evaluation method is to clarify whether or not a certain scheme is optimal under certain prioritized requirements. Therefore, the proposed method can help potential users of time stamping services select an appropriate one which meets their prioritized requirements. In this paper, we explain the basic idea of the evaluation method and show how to use it by applying it to seven existing schemes.

The encryption algorithm Camellia is a 128 bit block cipher proposed by NTT and Mitsubishi, Japan. Since the algebraic degree of the outputs after 3 rounds is greater than 128, designers estimate that it is impossible to attack Camellia by higher order differential. In this paper, we show a new higher order differential attack which controls the value of differential using proper fixed value of plaintext. As the result, we found that 6-round F-function can be attacked using 8th order differentials. The attack requires 217 chosen plaintexts and 222 F-function operations. Our computer simulation took about 2 seconds for the attack. If we take 2-R elimination algorithm, 7-round F-function will be attacked using 8th order differentials. This attack requires 219 chosen plaintexts and 264 F-function operations, which is less than exhaustive search for 128 bit key.

In cryptography, we want a Boolean function which satisfies PC(l) of order k for many (l,k). Let PCn(l,k) be a set of Boolean functions with n input bits satisfying PC(l) of order k. From a view point of construction, it is desirable that there exists (l0,k0) such that PCn(l0, k0) PCn(li,ki) for many i 1. In this paper, we show a negative result for this problem. We prove that PCn(l1,k1) PCn(l2,k2) for a large class of l1, k1, l2 and k2.

Many types of adaptive algorithms based on the MMSE criterion for co-channel interference suppression in DS/CDMA systems have been studied in great detail. However, these algorithms have such a problem that the training speed is greatly dropped under the strong near-far problem. In this paper, we propose and analyze an adaptive filter based on the Maximum Signal to Interference and Noise Ratio (MSINR) criterion, called adaptive MSINR filter. This filter is basically equivalent to the adaptive filter based on the MMSE criterion. However, due to the structual difference, the convergence speed is greatly improved. Specifically, the de-spreading vector in this filter is so renewed as to maximize the Signal to Interference and Noise Ratio (SINR) by minimizing the de-spread interference and noise power under the condition that the de-spread desired signal power keeps constant. So the proposed filter uses the estimated interference and noise signal calculated by subtracting the estimated desired signal from the received signal. It is just the reason why the adaptive MSINR filter shows remarkable convergence speed. And to satisfy the constant signal power condition, the projection matrix onto the orthogonal complement of the desired signal space is used for the de-spreading vector. For the proposed filter, we analyze the convergence modes and also investigate the de-spread interfernce and noise power for calculating the theoretical SINR curve. Then, we conduct some computer simulations in order to show the difference between this filter and the conventional one in terms of the SINR convergence speed. As the result, we confirm that the adaptive filter based on the MSINR criterion achieves significant progress in terms of the SINR convergence speed.

This paper presents a new sliding window algorithm that is well-suited to an elliptic curve defined over an extension field for which the Frobenius map can be computed quickly, e.g., optimal extension field. The algorithm reduces elliptic curve group operations by approximately 15% for scalar multiplications for a practically used curve in compared to Lim-Hwang's results presented at PKC2000, which was the fastest previously reported. The algorithm was implemented on computers. Scalar multiplication can be accomplished in 573 µs, 595 µs, and 254 µs on Pentium II (450 MHz), 21164A (500 MHz), and 21264 (500 MHz) computers, respectively.

This paper proposes a flexible tree-based key management framework for a terminal to connect with multiple content distribution systems (called as CDSs in this paper). In an existing tree-based key management scheme, a terminal keeps previously distributed node keys which are used for decrypting contents from a CDS. According to our proposal, the terminal can calculate its node keys of a selected CDS as the need arises, using the "public bulletin board" of the CDS. The public bulletin board is generated by a management center of the individual CDS, depending on a tree structure which it determines in its convenience. After the terminal calculates its node keys, it can get a content of the CDS using the calculated node keys.

A digit-recurrence algorithm for computing reciprocal square-root which appears frequently in multimedia and graphics applications is proposed. The reciprocal square-root is computed by iteration of carry-propagation-free additions, shifts, and multiplications by one digit. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the digit set, and etc. Details of a radix-2 version and a radix-4 version and designs of a floating-point reciprocal square-root circuit based on them are shown.

This paper describes fully integrated active guard band filters for suppressing the substrate coupling noise and their noise suppression effect measured by test chip experiments. The noise cancellation circuit of the active guard band filters simply consists of an inverter and a source follower. The substrate noise suppression effect was measured by using a test chip fabricated in a 0.18 µm CMOS triple-well process for system-on-a-chip. The noise with the filter was less than 5% of that without the filter and the noise suppression effect was observed from 1 MHz to 200 MHz by the statistical measurement of the voltage comparator. The noise suppression effect was also observed for actual digital switching noise produced by digital inverters. Configuration of the active guard band filter was investigated by simulation and it is shown that high and uniform noise suppression effect is achieved by placing the guard bands in the L-shape around the target triple-well area on the p-substrate.

OFDM transmission performance in mobile communications suffers severe degradation caused by multipath delay difference greater than the Guard Interval (GI). This is because the excess delay results in considerable Inter-Symbol Interference (ISI) between temporally adjacent symbols and Inter-Carrier Interference (ICI) among subcarriers in the same symbol. This paper proposes a robust OFDM receiver for the scattered pilot OFDM signal that can effectively suppress both ISI and ICI by using two types of equalization and a smoothed FFT-window. In order to verify the performance of the proposed receiver, computer simulations are conducted in accordance with the scattered pilot OFDM signal format of the Digital Terrestrial Television Broadcasting (DTTB). The simulation results demonstrate that the proposed receiver shows much better performance than the conventional receiver in multipath fading environments with the delay difference greater than GI duration.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

A postprocessing algorithm is presented for blocking artifact reduction in block-coded images using the adaptive filters along the pattern of neighborhood blocks. Blocking artifacts appear as irregular high-frequency components at block boundaries, thereby reducing the noncorrelation between blocks due to the independent quantization process of each block. Accordingly, block-adaptive filtering is proposed to remove such components and enable similar frequency distributions within two neighborhood blocks and a high correlation between blocks. This type of filtering consists of inter-block filtering to remove blocking artifacts at the block boundaries and intra-block filtering to remove ringing noises within a block. First, each block is classified into one of seven classes based on the characteristics of the DCT coefficient and MV (motion vector) received in the decoder. Thereafter, adaptive intra-block filters, approximated to the normalized frequency distributions of each class, are applied adaptively according to the various patterns and frequency distributions of each block as well as the filtering directions in order to reduce the blocking artifacts. Finally, intra-block filtering is performed on those blocks classified as complex to reduce any ringing noise without blurring the edges. Experimental tests confirmed the effectiveness of the proposed algorithm.

We introduce a clock schedule algorithm to obtain a clock schedule that achieves a shorter clock period and that can be realized by a light clock tree. A shorter clock period can be achieved by controlling the clock input timing of each register, but the required wire length and power consumption of a clock tree tends to be large if clock input timings are determined without considering the locations of registers. To overcome the drawback, our algorithm constructs a cluster that consists of registers with the same clock input timing located in a close area. The registers in each cluster are driven by a buffer and a shorter wire length can be achieved. In our algorithm, first registers are partitioned into clusters by their locations, and clusters are modified to improve the clock period while maintaining the radius of each cluster small. In our experiments, the clock period achieved in average is about 13% shorter than that achieved by a zero-skew clock tree, and about 4% longer than the theoretical minimum. The wire length and power consumption of a clock tree according to an obtained clock schedule is comparable to these of a zero skew tree.

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

In this paper, we present a novel algorithm to the alternative wiring problem by analyzing the implication relationship between nodes of alternative wires. Alternative wiring, or rewiring, refers to the process of adding a redundant connection to a circuit so as to make a target connection redundant and removable from the circuit without altering the functionality of the circuit. The well-known ATPG-based alternative wiring scheme, Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. But, the deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires. Our approaches of redundancy identification by source node and destination node implication relationship indicate that a large subset of unnecessary redundancy check processes can be further avoided to improve the efficiency significantly. We propose an algorithm, the Implication Based Alternative Wiring Logic Transformation (IBAW), to integrate the two adroit techniques. IBAW provides a competent solution to the alternative wiring problem and shows an outstanding efficiency in our experiments. Experiments were performed on MCNC benchmark circuits. Results show that IBAW runs 6.8 times faster than the original RAMBO in locating alternative wires and solution quality is maintained.

The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

This paper describes an automatic interface insertion scheme for in-system verification of algorithm models. To insert the interface, an algorithm model described in C is translated into another source code that includes the communication with hardware components in the target system to be validated with the algorithm model. The communication between the algorithm model and hardware components is achieved using transactors that perform transformation between access operations and bus cycle transactions. I/O terminal is introduced as an interface model to relate the transactions to access operations during the execution of the algorithm model, i.e., accesses to I/O terminals invoke bus cycle transactions in hardware and vice versa. An automatic interface insertion tool is developed using the source-to-source translation to identify the I/O terminals and insert interface function calls in the source code. The proposed automatic interface insertion scheme is validated by emulating several multimedia algorithms written in C on real target systems.

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

The existing methods for reconstruction of a super-resolution image from undersampled and shubpixel shifted image sequence have two disadvantages. One is that most of them have to perform a lot of computations which lead to taking a lot of time and cannot meet the need of realtime processing. Another is that they cannot achieve satisfactory results in the case that the undersampling rate is too low. This paper considers applying a pyramid structure method to the super-resolution of the image sequence since it has some iterative optimization and parallel processing abilities. Based on the Iterative Back-Projection proposed by Peleg, a practical implementation, called Pyramid Iterative Back-Projection, is presented. The experiments and the error analysis show the effectiveness of this method. The image resolution can be improved better even in the case of severely undersampled images. In addition, the proposed method can be done in parallel and meet the need of real-time processing. The implementation framework of the method can be easily extended to the other general super-resolution methods.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.

A basestation power amplifier requires high linearity and stable operation for common amplification of a multiplexed wideband signal. Nonlinearity compensation techniques with the feedforward or predistorter are useful for this purpose. This paper presents a predistortion amplifier with automatic control at RF band for application at a basestation. In this method, the predistorter distorts an RF input signal by referring to a look-up table (LUT) corresponding to the input power. Out-of-band radiation power are directly monitored at IF band to determine the LUT. A DSP with an iterative algorithm updates the content of the LUT to minimize the out-of-band radiation power. Computer simulation experiment is carried out. The use of this proposed method promises a highly linear wideband and high power-efficiency amplifier.