This is an attempt to examine the contact resistance of a composite material which is used for sliding contacts. The composite material used here is sintered by dispersing the solid lubricant WS2 into the metallic base alloy Cu-Sn. A method based on Greenwood's formula is applied to determine how the calculated values are related to the contact resistance values obtained in our experiments. As a result, the composite material mated with the carbon specimen is found nearly to corresponds to the values of those calculated by the extended Greenwood's formula, whereas its value mated with the tungsten specimen does not. In short, it is concluded that the composite material mated with the carbon specimen consists of multispots.

In this paper, we propose the media scheduler employing an adaptive estimator, which uses a posteriori information of data traffic characteristics to facilitate scheduling, when available, to provide on-line scheduling of dynamic scene change based on its statistical characteristics. Especially, a new adaptive scheduling scheme showed good persistent to the arrival message with bursty characteristics. And we confirmed the performance through the computer simulation when QOS requirements are given.

The performance of a nonblocking switch with two kinds of correlated input calls is analyzed. We define two kinds of calls as the waiting call and the immediate call, and assume that the immediate call has the priority over the waiting call. If the traffic density of one kind of calls is larger than maximum throughput, the ratio of the corresponding kind of calls to the total traffic must be restrained in some range. We derive the maximum ratio of the waiting call by using two approximate methods. The effects of traffic densities and transition probabilities of two kinds of calls on the maximum ratio of the waiting call are also considered. It is shown that, if the traffic density of the immediate call is smaller than that of the waiting call, our approximate methods are useful to derive the maximum ratio of the waiting call to the total traffic.

0.15 µm CMOS transistors have been fabricated. TiSi2 salicide was used for the gate electrode and source/drain to reduce parasitic resistance. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduce the junction capacitance, a reasonably short ring oscillator delay of 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution on the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effective for scaling the delay time and power consumption, because the source/drain size difficult to scale down to as small as the gate length.

This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

The main aim of device-level global routing is to obtain high-performance detailed routing under various layout constraints. This paper deals with global routing for analog function blocks. For analog LSIs, especially for those operating at high frequency, various layout constraints are specified prior to routing. Those constrainsts must be completely satisfied to achieve the required circuit performance. However, they are sometimes too hard to be solved by any heuristic method even if a problem is small in size. Thus, we propose a method based on the branch-and-bound algorithm, which can generate all possible solutions to find the best one. Unfortunately, the method tends to take a large amount of processing time. In order to defeat the drawbacks by accelerating the process, constraints are classified into two groups: constraints on single nets and constraints between two nets. Therefore our method consists of two parts: in the first part only constraints on single nets are processed and in the second part only constraints between two nets are processed. The method is efficient because many possible routes that violate layout constraints are rejected immediately in each part. This makes it possible to construct a smaller search tree and to reduce processing time. Additionally this idea, all nets processed in the second phase are sorted in the proper order to reduce the number of edges in the search tree. This saves much processing time, too. Experimental results show that our method can find a good global route for hard layout constraints in practical processing time, and also show that it is superior to the well-known simulated annealing method both in quality of solutions and in processing time.

This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle cycle time optimization. We also make a useful initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it can speed up a 13k-transistor circuit of a manual chip design by 17% without any increase of area.

We give an efficient shortest path algorithm on a mesh-connected processor array for nn banded matrices with bandwidth b. We use a b/2b/2 semisystolic processor array. The input data is supplied to the processor array from the host computer. The output from the processor array can be also supplied to itself through the host computer. This algorithm computes all pair shortest distances within the band in 7n4b/21 steps.

We model a road network as a directed graph G(V,E) with a source s and a sink t, where each edge e has a positive length l(e) and each vertex v has a distribution function αv with respect to the traffic entering and leaving v. This paper proposes a polynomial time algorithm for evaluating the importance of each edge e E whicn is defined to be the traffic f(e) passing through e in order to assign the required traffic Fst(0) from s to t along only shortest s-t paths in accordance with the distribution function αv at each vertex v.

In this paper, we propose a hybrid hierarchical global router for multi-layer VLSI's, which executes routing and layering simultaneously. This novel approach, a hybrid hierarchical global router, is a combination of a topdown and a bottomup hierarchical routers, and may be one of interesting routing techniques. We also show experimental results, which demonstrate the superiority of the hybrid hierarchical approach. This approach may have many possibilities to be used in a various fields.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

Recently as one of attractive applications in the B-ISDN era, LAN/MAN interconnection through an ATM network has been coming up because burstiness of LAN/MAN data traffic is applicable to distinctive features of cell based ATM network. In order to overcome a difference of the connection mode, i.e., CL packet transfer of LAN/MAN and CO cell transfer of ATM network, a number of interworking and bandwidth allocation mechanisms have been proposed. These methods, however, indicate both merits and drawbacks concerning with CL data transfer quality, network resource efficiency and processing overhead in IWU/CLS and the network, and have been mostly evaluated only for a single IWU model. This paper aims at showing the most appropriate method of LAN/MAN interworking for IWU-IWU or IWU-CLSF connection. In the paper, some interworking issues including a general qualitative assessment are clarified. We then evaluate the selected five interworking methods based on Bandwidth Renegotiation (BR) and VC Establishment (VCE), which are combined with Traffic Enforcement Functions (TEFs) based on policing mechanisms and Cell Loss Control (CLC) scheme. By transient and stationary simulation approach for a single IWU and an IWU-CLS connection model, the most applicable method is indicated as a case study from view points of the communication quality, effective use of the bandwidth and processing load.

Circuit access control is a traffic control technique of rejecting calls arriving at a group of specified circuits to make the group free at a target scheduled time so that the capacity may be dynamically reallocated to serve other traffic demand. This technique plays an important role for resource allocation control in state-of-the-art capacity reconfigurable networks as well as for switching calls on a reserved basis in the ISDNs. In this paper, we present a novel adaptive scheme for circuit access control in order to overcome the inefficiency of the conventional deterministic scheme. The presented scheme is based only on knowledge about service time and bandwidth characteristics of calls. The transitional behavior of the circuit group under the scheme is analyzed, and the gain in utilization achieved by the adaptive scheme is examined. We treat a model of the circuit group shared by multi-slot calls with different service times, and describe the results of the transient analysis and the approximation method for evaluating the gains.

This paper describes an optimal scheduling approach which finds the scheduling result of the minimum functional unit cost under the given timing constraint. In this method, a well-defined search space is constructed incrementally and traversed in a branch-and-bound manner. During the traversal, tighter lower bounds are estimated and utilized coupled with the upper bound on the optimal solution in pruning the search space effectively. This method is extended to support multi-cycling operations, operation chaining, pipelined functional units, and pipelined data paths. Experimental results on some benchmarks show the efficiency of the proposed approach.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

In this paper, we demonstrate how Yamakawa's chaotic chips and Chua's circuits can be used to implement a secure communication system. Furthermore, their performance for the secure communication is discussed.

The blazing effects of dielectric grating consisting of two adjacent sinusoidally modulated layers which lead to the asymmetric profiles on a substrate are analyzed by using improved Fourier series expansion method. This method can be applied to the wide range of grating structure and gave high accurate results by comparing with those obtained by previous method. In this paper, the efficient blazing effects can be achieved by varying normalized distance (w/p) and the normalized thickness (d1/D), where D is kept fixed. The results are greater than those of trapezoidal profiles and triangular profiles. The influences of the second order of modulation index on the radiation efficiencies and normalized leakage factor are also discussed.

In this report, we propose a robust block adaptive digital filter (BADF) which can improve the accuracy of the estimated weights by averaging the adaptive weight vectors. We show that the improvement of the estimated weights is independent of the input signal correlation.

A scalable and flexible ASIC CIM system distributed on UNIX workstations, ORCHARD , has been developed. It is designed from three viewpoints: (1) cost and TAT reduction in system construction, (2) flexibility in data management for quality control, and (3) precise and quick scheduling and effective lot tracking to control TAT for each lot. The concept of a "virtual machine" is introduced to connect equipment having various protocols to a host system. The virtual machine is automatically generated at an average automatic generation ratio of as high as 89%, which leads to a reduction in cost and TAT in system construction. Data for quality control is managed by changing flexibly the "data processing recipe." This recipe defines screen format, data collected from equipment, and data transfered from various databases. Precise scheduling of lots with various levels of priority is achieved by introducing a priority evaluation function, thereby reducing scheduling time to 1/20 that for manual scheduling.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.