This letter proposes a transmission scheme called spatial vector (SV), which is effective for Nakagami-m fading multiple-input multiple-output channels. First, the analytical error rate of SV is derived for Nakagami-m fading MIMO channels. Next, an example of SV called integer SV (ISV) is introduced. The error performance was evaluated over Nakagami-m fading from m = 1 to m = 50 and compared with spatial modulation (SM), enhanced SM, and quadrature SM. The results show that for m > 1, ISV outperforms the SM schemes and is robust to m variations.

There have been some researchers that investigate the accuracy of the approximation to a function that shows a generating pattern of data by a deep neural network. However, they have confirmed only whether at least one function close to the function showing a generating pattern exists in function classes of deep neural networks whose parameter values are changing. Therefore, we propose a new criterion to infer the approximation accuracy. Our new criterion shows the existence ratio of functions close to the function showing a generating pattern in the function classes. Moreover, we show a deep neural network with a larger number of layers approximates the function showing a generating pattern more accurately than one with a smaller number of layers under the proposed criterion, with numerical simulations.

Environmental power generation devices such as solar cells are used as power sources for IoT devices. Due to the large internal resistance of such power source, LSIs in the IoT devices may malfunction when the LSI operates at high speed, a large current flows, and the voltage drops. In this paper, a standard cell library of stacked structured cells is proposed to increase the delay of logic circuits within the range not exceeding the clock cycle, thereby reducing the maximum current of the LSIs. We show that the maximum power consumption of LSIs can be reduced without increasing the energy consumption of the LSIs.

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.

Double modular redundancy (DMR) is to execute an operation twice and detect a soft error by comparing the duplicated operation results. The soft error is corrected by re-executing necessary operations. The re-execution requires error-free input data and registers are needed to store such necessary error-free data. In this paper, a method to minimize the required number of registers is proposed where an appropriate subgraph partitioning of operation nodes are searched. In addition, using the proposed register minimization method, a minimization of the area of functional units and registers required to implement the DMR design is proposed.

With the demand for energy-efficient and high- performance computing, multicore architecture has become more appealing than ever. Multicore task scheduling is one of domains in parallel computing which exploits the parallelism of multicore. Unlike traditional scheduling, multicore task scheduling has recently been studied on the assumption that tasks have inherent parallelism and can be split into multiple sub-tasks in data parallel fashion. However, it is still challenging to properly determine the degree of parallelism of tasks and mapping on multicores. Our proposed scheduling techniques determine the degree of parallelism of tasks, and sub-tasks are decided which type of cores to be assigned to heterogeneous multicores. In addition, two approaches to hardware/software codesign for heterogeneous multicore systems are proposed. The works optimize the types of cores organized in the architecture simultaneously with scheduling of the tasks such that the overall energy consumption is minimized under a deadline constraint, a warm start approach is also presented to effectively solve the problem. The experimental results show the simultaneous scheduling and core-type optimization technique remarkably reduces the energy consumption.

In the field of reliability engineering, many studies on the relationship of reliability between components and the entire system have been conducted since the 1960s. Various properties of large-scale systems can be studied by limit theorems. In addition, the limit theorem can provide an approximate system reliability. Existing studies have established the limit theorems of a connected-(r, s)-out-of-(m, n):F lattice system consisting of components with the same reliability. However, the existing limit theorems are constrained in terms of (a) the system shape and (b) the condition under which the theorem can be applied. Therefore, this study generalizes the existing limit theorems along the two aforementioned directions. The limit theorem established in this paper can be useful for revealing the properties of the reliability of a large-scale connected-(r, s)-out-of-(m, n):F lattice system.

The newly proposed orthogonal time frequency space (OTFS) system exhibits excellent error performance on high-Doppler fading channels. However, the rectangular prototype window function (PWF) inherent in OTFS leads to high out-of-band emission (OOBE), which reduces the spectral efficiency in multi-user scenarios. To this end, this paper presents an OTFS system based on bi-orthogonal frequency division multiplexing (OTFS-BFDM) modulation. In OTFS-BFDM systems, PWFs with bi-orthogonal properties can be optimized to provide lower OOBE than OTFS, which is a special case with rectangular PWF. We further derive that the OTFS-BFDM system is sparsely-connected so that the low-complexity message passing (MP) decoding algorithm can be adopted. Moreover, the power spectral density, peak to average power ratio (PAPR) and bit error rate (BER) of the OTFS-BFDM system with different PWFs are compared. Simulation results show that: i) the use of BFDM modulation significantly inhibits the OOBE of OTFS system; ii) the better the frequency-domain localization of PWFs, the smaller the BER and PAPR of OTFS-BFDM system.

At Eurocrypt 2011, Lindell presented practical static and adaptively UC-secure commitment schemes based on the DDH assumption. Later, Blazy et al. (at ACNS 2013) improved the efficiency of the Lindell's commitment schemes. In this paper, we present static and adaptively UC-secure commitment schemes based on the same assumption and further improve the communication and computational complexity, as well as the size of the common reference string.

This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.

The problem of enumerating connected induced subgraphs of a given graph is classical and studied well. It is known that connected induced subgraphs can be enumerated in constant time for each subgraph. In this paper, we focus on highly connected induced subgraphs. The most major concept of connectivity on graphs is vertex connectivity. For vertex connectivity, some enumeration problem settings and enumeration algorithms have been proposed, such as k-vertex connected spanning subgraphs. In this paper, we focus on another major concept of graph connectivity, edge-connectivity. This is motivated by the problem of finding evacuation routes in road networks. In evacuation routes, edge-connectivity is important, since highly edge-connected subgraphs ensure multiple routes between two vertices. In this paper, we consider the problem of enumerating 2-edge-connected induced subgraphs of a given graph. We present an algorithm that enumerates 2-edge-connected induced subgraphs of an input graph G with n vertices and m edges. Our algorithm enumerates all the 2-edge-connected induced subgraphs in O(n3m|SG|) time, where SG is the set of the 2-edge-connected induced subgraphs of G. Moreover, by slightly modifying the algorithm, we have a O(n3m)-delay enumeration algorithm for 2-edge-connected induced subgraphs.

To safeguard critical services and assets in a distributed environment, collaborative intrusion detection systems (CIDSs) are usually adopted to share necessary data and information among various nodes, and enhance the detection capability. For simplifying the network management, software defined networking (SDN) is an emerging platform that decouples the controller plane from the data plane. Intuitively, SDN can help lighten the management complexity in CIDSs, and a CIDS can protect the security of SDN. In practical implementation, trust management is an important approach to help identify insider attacks (or malicious nodes) in CIDSs, but the challenge is how to ensure the data integrity when evaluating the reputation of a node. Motivated by the recent development of blockchain technology, in this work, we design BlockCSDN — a framework of blockchain-based collaborative intrusion detection in SDN, and take the challenge-based CIDS as a study. The experimental results under both external and internal attacks indicate that using blockchain technology can benefit the robustness and security of CIDSs and SDN.

In flat panel display (FPD) lithography, a high resolution and large depth of focus (DOF) are required. The demands for high throughput have necessitated the use of large glass plates and exposure areas, thereby increasing focal unevenness and reducing process latitude. Thus, a large DOF is needed, particularly for high-resolution lithography. To manufacture future high-definition displays, 1.0μm line and space (L/S) is predicted to be required, and a technique to achieve this resolution with adequate DOF is necessary. To improve the resolution and DOF, resolution enhancement techniques (RETs) have been introduced. RETs such as off-axis illumination (OAI) and phase-shift masks (PSMs) have been widely used in semiconductor lithography, which utilizes narrowband illumination. To effectively use RETs in FPD lithography, modification for broadband illumination is required because FPD lithography utilizes such illumination as exposure light. However, thus far, RETs for broadband illumination have not been studied. This study aimed to develop techniques to achieve 1.0μm L/S resolution with an acceptable DOF. To this end, this paper proposes a method that combines our previously developed RET, namely, divided spectrum illumination (DSI), with an attenuated PSM (Att. PSM). Theoretical observations and simulations present the design of a PSM for broadband illumination. The transmittance and phase shift, whose degree varies according to the wavelength, are determined in terms of aerial image contrast and resist loss. The design of DSI for an Att. PSM is also discussed considering image contrast, DOF, and illumination intensity. Finally, the exposure results of 1.0μm L/S using DSI and PSM techniques are shown, demonstrating that a PSM greatly improves the resist profile, and DSI enhances the DOF by approximately 30% compared to conventional OAI. Thus, DSI and PSMs can be used in practical applications for achieving 1.0μm L/S with sufficient DOF.

In this letter, firstly, a novel adaptive beamformer using independent component analysis (ICA) algorithm is proposed. By this algorithm, the ambiguity of amplitude and phase resulted from blind source separation is removed utilizing the special structure of array manifolds matrix. However, there might exist great calibration error when the powers of interferences are far larger than that of desired signal at many applications such as sonar, radio astronomy, biomedical engineering and earthquake detection. As a result, this will lead to a significant reduction in separation performance. Then, a new method based on the combination of ICA and primary component analysis (PCA) is proposed to recover the desired signal's amplitude under strong interference. Finally, computer simulation is carried out to indicate the effectiveness of our methods. The simulation results show that the proposed methods can obtain higher SNR and more accurate power estimation of desired signal than diagonal loading sample matrix inversion (LSMI) and worst-case performance optimization (WCPO) method.

In-band full-duplex (IBFD) has been an attractive technology, which can theoretically double the spectral efficiency. However, when performing IBFD in the dynamic-duplex cellular (DDC) system, inter-user interference (IUI) deteriorates transmission performance in downlink (DL) communication and limits IBFD-applicable area and IBFD application ratio. In this paper, to expand the IBFD-applicable area and improve the IBFD application ratio, we propose an IUI reduction scheme using successive interference cancellation (SIC) for the DDC system. SIC can utilize the power difference and reduce the signal with the higher power. The effectiveness of the proposed scheme is evaluated by the computer simulation. The IUI reducing effect on the IBFD-inapplicable area is confirmed when the received power of the IUI is stronger than that of the desired signal at the user equipment for DL (DL-UE). The IBFD-inapplicable area within 95m from the DL-UE, where the IBFD does not work without the proposed scheme, can reduce by 43.6% from 52.8% to 9.2% by applying the proposed scheme. Moreover, the IBFD application ratio can improve by 24.6% from 69.5% to 94.1%.

The development of educational informatization makes data privacy particularly important in education. With society's development, the education system is complicated, and the result of education evaluation becomes more and more critical to students. The evaluation process of education must be justice and transparent. In recent years, the Onscreen Marking (OSM) system based on traditional cloud platforms has been widely used in various large-scale public examinations. However, due to the excessive concentration of power in the existing scheme, the mainstream marking process is not transparent, and there are hidden dangers of black-box operation, which will damage the fairness of the examination. In addition, issues related to data security and privacy are still considered to be severe challenges. This paper deals with the above problems by providing secure and private transactions in a distributed OSM assuming the semi-trusted examination center. We have implemented a proof-of-concept for a consortium blockchain-based OSM in a privacy-preserving and auditable manner, enabling markers to mark on the distributed ledger anonymously. We have proposed a distributed OSM system in high-level, which provides theoretical support for the fair evaluation process of education informatization. It has particular theoretical and application value for education combined with blockchain.

Many cloud service providers employ specialized hardware accelerators, called neural processing units (NPUs), to accelerate deep neural networks (DNNs). An NPU scheduler is responsible for scheduling incoming user requests and required to satisfy the two, often conflicting, optimization goals: maximizing system throughput and satisfying quality-of-service (QoS) constraints (e.g., deadlines) of individual requests. We propose Layerweaver+, a low-cost layer-wise DNN scheduler for NPUs, which provides both high system throughput and minimal QoS violations. For a serving scenario based on the industry-standard MLPerf inference benchmark, Layerweaver+ significantly improves the system throughput by up to 266.7% over the baseline scheduler serving one DNN at a time.

Neural network-based three-dimensional (3D) reconstruction methods have produced promising results. However, they do not pay particular attention to reconstructing detailed parts of objects. This occurs because the network is not designed to capture the fine details of objects. In this paper, we propose a network designed to capture both the coarse and fine details of objects to improve the reconstruction of the fine parts of objects.

With the development of Internet technology, the demand for signing electronic contracts has been greatly increased. The electronic contract generated by the participants in an online way enjoys the same legal effect as paper contract. The fairness is the key issue in jointly signing electronic contracts by the involved participants, so that all participants can either get the same copy of the contract or nothing. Most existing solutions only focus on the fairness of electronic contract generation between two participants, where the digital signature can effectively guarantee the fairness of the exchange of electronic contracts and becomes the conventional technology in designing the contract signing protocol. In this paper, an efficient blockchain-based multi-party electronic contract signing (MECS) protocol is presented, which not only offers the fairness of electronic contract generation for multiple participants, but also allows each participant to aggregate validate the signed copy of others. Security analysis shows that the proposed MECS protocol enjoys unforgeability, non-repudiation and fairness of electronic contracts, and performance analysis demonstrates the high efficiency of our construction.

Construction of multiple output functions is one of the most important problems in the design and analysis of stream ciphers. Generally, such a function has to be satisfied with several criteria, such as high nonlinearity, resiliency and high algebraic degree. But there are mutual restraints among the cryptographic parameters. Finding a way to achieve the optimization is always regarded as a hard task. In this paper, by using the disjoint linear codes and disjoint spectral functions, two classes of resilient multiple output functions are obtained. It has been proved that the obtained functions have high nonlinearity and high algebraic degree.