Non-malleability is an important security property of commitment schemes. The property means security against the man-in-the-middle attack, and it is defined and proved in the simulation paradigm using the corresponding simulator. Many known non-malleable commitment schemes have the common drawback that their corresponding simulators do not work in a straight-line manner, requires rewinding of the adversary. Due to this fact, such schemes are proved non-malleable only in the stand-alone cases. In the multiple-instances setting, i.e., when the scheme is performed concurrently with many instances of itself, such schemes cannot be proved non-malleable. The paper shows an efficient commitment scheme proven to be non-malleable even in the multiple-instances setting, based on the KEA1 and DDH assumptions. Our scheme has a simulator that works in a straight-line manner by using the KEA1-extractor instead of the rewinding strategy.

The ESIGN signature scheme was initially proposed in 1985. Since then, several variants have been proposed, but only a few have been formally supported using the methodology of provable security. In addition, these schemes are different from the ESIGN-PSS signature scheme submitted to ISO/IEC-14888-2 for standardization. It is believed that ESIGN-PSS is secure against the chosen-message attack, however, there has not yet been any report verifying this belief. This paper presents the security proofs of ESIGN-PSS and a variant of this scheme, denoted ESIGN-PSS-R, which is a signature scheme comprising the ESIGN signature mechanism and the PSS-R mechanism.

This paper describes miniaturized broadband lumped-element in-phase power dividers. We first propose two types of miniaturized broadband lumped-element in-phase power dividers composed of two inductors, a resistor, and two capacitors. Next, we use a simulation to compare these dividers with conventional power dividers. The simulation results reveal that the proposed lumped-element in-phase power dividers can help miniaturize circuits (by decreasing inductances by about 30%, reducing the number of necessary capacitors by half, and decreasing necessary capacitances by about 30% as compared to conventional lumped-element dividers) and attain broadband frequency characteristics (by increasing normalized operating frequency bandwidths (f/f0) by about 80% as compared to conventional lumped-element dividers).

In this paper, we derive state equations for linearized discrete-time models of forth-order charge-pump phase-locked loops. We solve the differential equations of the loop filter by using the initial conditions and the boundary conditions in a period. The solved equations are linearized and rearranged as discrete-time state equations for checking stability conditions. Some behavioral simulations are performed to verify the proposed method. By examining the stability of loops with different conditions, we also propose an expression between the lower bound of the reference frequency, the open loop unit gain bandwidth, and the phase margin.

In this paper, we describe a novel focusing mechanism that uses a varifocal mirror and its application to measuring the shape of solder bumps arrayed on an LSI package board based on the shape-from-focus technique. We used a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror to build a simple yet fast focusing mechanism. The varifocal mirror was situated at the focal point of the image-taking lens in image space so that the lateral magnification was constant during focusing and an orthographic projection was perfectly established. The focused plane could be shifted along the optical axis with a precision of 1.4 µm in a depth range of 1.3 mm by driving the varifocal mirror. A magnification of 1.97 was maintained during focusing. Evaluating the curvature of field and removing its effect from the depth data reduced errors. The shapes of 208 solder bumps, 260 µm high and arrayed at a pitch of 500 µm on the board, were measured. The entire 10 mm10 mm board was segmented into 34 partly overlapping sections. We captured 101 images in each section with a high-resolution camera at different focal points at 15 µm intervals. The shape of almost the entire upper hemisphere of a solder bump could be measured. The error in measuring the bump heights was less than 12 µm.

ID-SP-M4M scheme means ID-based series-parallel multisignature schemes for multi-messages. In this paper, we investigate series-parallel multisignature schemes for multi-messages and propose an ID-SP-M4M scheme based on pairings in which signers in the same subgroup sign the same message, and those in different subgroups sign different messages. Our new scheme is an improvement over the series-parallel multisignature schemes introduced by Doi et al.[6]-[8] and subsequent results such as the schemes proposed by Burmester et al.[4] and the original protocols proposed by Tada [20],[21], in which only one message is to be signed. Furthermore, our ID-SP-M4M scheme is secure against forgery signature attack from parallel insiders under the BDH assumption.

Kurosawa-Desmedt public-key encryption scheme is a variation of Cramer-Shoup public-key encryption schemes, which are the first practical schemes secure against adaptive chosen ciphertext attack (IND-CCA) in standard model. We introduce some variants of Kurosawa-Desmedt public-key encryption scheme which are also IND-CCA secure. Furthermore, the variants are either more efficient or less cryptographic assumptions than the original version.

A second order charge pump (SOCP) scheme is proposed in this letter. Compared with the conventional single charge pump, the second order charge pump does not suffer phase errors caused by the output voltage dependent current mismatches. Also, the second order charge pump can be implemented in a mixed-mode type, enabling the fast lock and the various operation modes simultaneously. The proposed SOCP has been adopted into the duty cycle corrector (DCC) loops of DDR2 DRAM, and shows a much widened correction range owing to the removal of the parasitic effects.

This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.

We demonstrate a fast shutdown and resumption of a logic circuit applied a nonvolatile latch having SrBi2(Ta,Nb)2O9 (SBT) capacitors without a higher drive voltage than a logic voltage of 1.8 V. By assigning an individual drive circuit of the SBT capacitors to the nonvolatile latch not sharing a drive circuit with multiple nonvolatile latches, the fast shutdown and resumption of a logic circuit were completed in 7.5 ns at a drive voltage of 1.3 V. The fast shutdown and resumption without an addition of a high drive voltage to a logic circuit meets a requirement from power-saving applications of system LSIs fabricated in CMOS technologies at 90-nm and below.

In difficult classification problems of the z-dimensional points into two groups giving 0-1 responses due to the messy data structure, we try to find the denser regions for the favorable customers of response 1, instead of finding the boundaries to separate the two groups. Such regions are called the bumps, and finding the boundaries of the bumps is called the bump hunting. The main objective of this paper is to find the largest region of the bumps under a specified ratio of the number of the points of response 1 to the total. Then, we may obtain a trade-off curve between the number of points of response 1 and the specified ratio. The decision tree method with the Gini's index will provide the simple-shaped boundaries for the bumps if the marginal density for response 1 shows a rather simple or monotonic shape. Since the computing time searching for the optimal trees will cost much because of the NP-hardness of the problem, some random search methods, e.g., the genetic algorithm adapted to the tree, are useful. Due to the existence of many local maxima unlike the ordinary genetic algorithm search results, the extreme-value statistics will be useful to estimate the global optimum number of captured points; this also guarantees the accuracy of the semi-optimal solution with the simple descriptive rules. This combined method of genetic algorithm search and extreme-value statistics use is new. We apply this method to some artificial messy data case which mimics the real customer database, showing a successful result. The reliability of the solution is discussed.

The concept of M-convex functions has recently been generalized for functions defined on constant-parity jump systems. The b-matching problem and its generalization provide canonical examples of M-convex functions on jump systems. In this paper, we propose a steepest descent algorithm for minimizing an M-convex function on a constant-parity jump system.

Group signature schemes with membership revocation have been intensively researched. However, signing and/or verification of some existing schemes have computational costs of O(R), where R is the number of revoked members. Existing schemes using a dynamic accumulator or a similar technique have efficient signing and verifications with O(1) complexity. However, before signing, the signer has to modify his secret key with O(N) or O(R) complexity, where N is the group size. Therefore, for larger groups, signers suffer from enormous costs. On the other hand, an efficient scheme for middle-scale groups with about 1,000 members is previously proposed, where the signer need not modify his secret key. However this scheme also suffers from heavy signing/verification costs for larger groups with more than 10,000 members. In this paper, we adapt the middle-scale scheme to larger groups ranging from 1,000 to 1,000,000 members. At the sacrifice of the group manager's slight cost, our signing/verification is sufficiently efficient.

Bi-stable displays form the foundation of a novel and attractive LCD technology. From now on, images can be maintained on the LCD after driving voltages have been withdrawn from the electrodes. In low frame-rate applications such as e-books, e-labels, smartcards etc., this offers a major improvement in power consumption and battery life. However, bi-stable displays require high driving voltages and complex waveforms. Furthermore, the nature of some applications doesn't allow the use of relatively large passive components. This rules out more traditional approaches for high-voltage generation with external coils or capacitors. This paper describes the design of completely integrated and programmable high-voltage generators capable of generating output voltages up to 50 V out of a 3 V supply voltage. Features like 8-bit output voltage programmability and stabilisation were implemented to make this type of high-voltage generator suitable for bi-stable display drivers. Design aspects and simulation results are discussed, as well as measurements on prototype generators implemented in the 0.7 µm 100 V I2T100 technology from AMI Semiconductor.

In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phase-locked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-µm CMOS process. The power consumption is 3 mW and the die area is 0.270.3 mm2.

This paper proposes a set of novel distributed algorithms on m-D mesh overlay configurations for short delay and low resource consumption application layer multicast. In contrast to previous approaches, our application layer multicast adopts two-layer tree architecture and the novelty and contribution are: (1) cluster formation algorithm assigns the closest group members into the same cluster that greatly decreases the multicast delay and resource consumption caused by the message transmission among the members with long distances; (2) optimal core selection algorithm seeks the cluster member who has the minimum sum of static delay distances to other cluster members as the optimal cores (i.e. cluster cores) that guarantees the short multicast delay; (3) weighted shortest path tree generation algorithm constructs a shortest path tree rooted at the optimal core for each cluster. The shortest path tree utilizes the minimum sum of links that are on the shortest paths among the cluster members; and (4) distributed multicast routing algorithm directs the multicast messages to be efficiently distributed along the two-layer multicast architecture in parallel without a global control. The extended simulation results indicate that the application layer multicast constructed by our algorithms is efficient in terms of short multicast delay and low network resource consumption as compared with other well-known existing multicast solutions.

A coplanar type lumped-element 6-pole microwave Chebyshev bandpass filter (BPF) of center frequency (f0) 2.0 GHz and fractional bandwidth (FBW) 1.0 % was designed. For the design method, theory of direct coupled resonator filters using K-inverters was employed. Coplanar type lumped-element BPFs are composed of a meander-line L and interdigital C elements. The frequency response was simulated and analyzed using an electromagnetic field simulator (Sonnet-EM). Further, the changes in f0 and FBW of the BPF were also realized by the mechanical tuning method.

In this paper authorization-limited transformation-free proxy cryptosystems (AL-TFP systems) are studied. It is a modification of the original proxy cryptosystem introduced by Mambo et al.[8] in which a ciphertext transformation by the original decryptor is necessary, and also a modification of the delegated decryption system proposed by Mu et al.[10]. In both systems proposed in [8] and [10], the original decryptors have to trust their proxies completely. The AL-TFP system allows the proxy decryptor to do decryption directly without any ciphertext transformation from the original decryptor, so that it can release the original decryptor more efficiently from a large amount of decrypting operations. Moreover, the original decryptor's privacy can be protected efficiently because the authority of proxy decryptor is limited to his duty and valid period. An active identity-based and a directory-based AL-TFP systems from pairings are proposed. Furthermore, an application of directory-based AL-TFP system to electronic commerce is also described. The securities of our schemes introduced are based on the BDH assumption.

In this letter, the validity of lumped element class-F amplifier circuit design approaches, which were previously proposed by the same authors, has been demonstrated experimentally using microwave InGaP/GaAs HBT. By means of the proposed class-F amplifier design method, more than 4th order higher harmonic frequencies can be taken into account in class-F microwave amplifier design using only lumped element components. In this approach, miniaturization of class-F amplifier circuit has also been realized. A collector efficiency of 71.2% and a power-added efficiency of 69.2% have been measured at an operating fundamental frequency of 1 GHz considering up to the 4th order higher harmonic frequency.

When an embedded system is designed, system performance and power consumption have to be taken carefully into consideration. In this paper, we focus on reducing the number of memory access times in embedded systems to improve performance and save power. We use the locality of running programs to reduce the number of memory accesses in order to save power and maximize the performance of an embedded system. We use shorter code words to encode the instructions that are frequently executed and then pack continuous code words into a pseudo instruction. Once the decompression engine fetches one pseudo instruction, it can extract multiple instructions. Therefore, the number of memory access times can be efficiently reduced because of space locality. However, the number of the most frequently executed instructions is different due to the program size of different applications; that is, the number of memory access times increases when there are less encoded instructions in a pseudo instruction. This situation results in a degradation of system performance and power consumption. To solve this problem, we also propose the use of multiple reference tables. Multiple reference tables will result in the most frequently executed instructions having shorter encoded code words, thereby improving the performance and power of an embedded system. From our simulation results, our method reduces the memory access frequency by about 60% when a reference table with 256 instructions is used. In addition, when two reference tables that contain 256 instructions each are used, the memory access ratio is 10.69% less than the ratio resulting from one reference table with 512 instructions.