Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.

With Wireless Sensor Networks (WSNs) involving in diverse applications, the realistic analysis of energy consumption of a sensor node in an error-prone network environment is emerging as an elementary research issue. In this paper, we introduce a Distributed Communication Model (DCM) that can accurately determine the energy consumption through data communication from source to destination in error-prone network environments. The energy consumption is affected with the quality of link, which is characterized by symmetry, directivity, instability, and irregularity of the communication range of a sensor node. Due to weak communication links, significant packet loss occurs that affects the overall energy consumption. While other models unable to determine energy consumption due to lossy links in error-prone and unstable network environments, DCM can accurately estimate the energy consumption in such situations. We also perform comprehensive analysis of overheads caused by data propagation through multi-hop distributed networks. We validate DCM through both simulations and experiments using MICAz motes. Similarity of the results from energy consumption analysis with both simulations and experimentations shows that DCM is realistic, compared to other models in terms of accuracy and diversity of the environments.

A mobile station (MS) in an IEEE 802.16e network manages its limited energy using the sleep mode operation. An MS can power down its physical operation components during the unavailability interval of the sleep mode. To reduce energy consumption by increasing the unavailability interval, this paper proposes an enhanced power saving mechanism (ePSM) when both activated Type I and Type II power saving classes (PSCs) exist in an MS. A performance evaluation confirms that ePSM results in the improved performance in terms of the unavailability interval as well as the energy consumption than conventional schemes.

Reducing the energy consumption of wireless communication systems with new technologies and solutions continues to be an important concern in developing future standards. In this paper, we study the routing strategies in multi-hop relaying networks. For a 2-way assignment routing method, an efficient feedback scheme is presented to minimize the power consumption over the whole system. Compared with the full channel information in traditional feedback scheme, only the backward accumulated feedback metrics are required. If the proposed routing calculation is used, there is no performance loss. When the number of the hops and the relays is large, the new scheme achieves a significant feedback overhead reduction. Moreover, we show a proof for the optimality of the presented routing strategy based on mathematical induction.

This paper presents a current-reused quadrature voltage-controlled oscillator (QVCO) which adopts a source-connection coupling structure. The QVCO simultaneously achieves low phase noise and low power consumption by newly combining current-reused VCOs and coupling transistors. The measured QVCO obtains good FoM of -188.2 dBc at a frequency of 2.2 GHz with 3.96 mW power consumption.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

This paper proposes a technique for two-stage operational amplifiers (OPAMPs) to optimize power consumption according to various channel conditions of wireless communication systems. The proposed OPAMP has the ability of reducing the quiescent current of each stage independently by introducing additional common-mode feedback, therefore more optimization is possible according to the channel conditions than conventional two-stage OPAMPs. The simulations verify the benefits of the technique. As a proof-of-concept topology, the proposed OPAMPs were used in a channel-selection filter for a multi-standard mobile-TV receiver. The power consumption of the filter, 3.4–5.0 mW, was adjustable according to the bandwidth, the noise, and the jammer level. The performance of the filter meets the requirements and verifies the effectiveness of the proposed approach. The filter was fabricated in 0.18-µm CMOS and occupied 0.64 mm2.

An area efficiency hybrid decoupling scheme is proposed to suppress the charge pump noise during F-N tunneling program in non-volatile memory (NVM). The proposed scheme is focused on suppressing the average noise power in frequency domain aspect, which is more suitable for the program error reduction in NVMs. The concept of active capacitor is utilized. Feed forward effect of the amplifier is firstly considered in the impedance analysis, and a trade-off relation between in-band and out-band frequency noise decoupling performance is shown. A fast optimization based on average noise power is made to achieve minimum error in the F-N tunneling program. Simulation results show very stable output voltage in different load conditions, the average ripple voltage is 17 mV with up to 20 dB noise-suppression-ratio (NSR), and the F-N tunneling program error is less than 5 mV for a 800 µs program pulse. A test chip is also fabricated in 0.18 µm technology. The area overhead of the proposed scheme is 2%. The measurement results show 24.4 mV average ripple voltage compared to 72.3 mV of the conventional one with the same decoupling capacitance size, while the noise power suppression achieves 15.4 dB.

Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

The Internet is an extremely convenient network and has become one of the key infrastructures for daily life. However, it suffers from three serious problems; its structure does not suit traffic centralization, its power consumption is rapidly increasing, and its round-trip time (RTT) and delay jitter are large. This paper proposes an extremely energy efficient layer-3 network architecture for the future Internet. It combines the Service Cloud with the Cloud Router and application servers, with the Optical Aggregation Network realized by optical circuit switches, wavelength-converters, and wavelength-multiplexers/demultiplexers. User IP packets are aggregated and transferred through the Optical Aggregation Network to Cloud transparently. The proposed network scheme realizes a network structure well suited to traffic centralization, reduces the power consumption to 1/20-1/30 compared to the existing Internet, reduces the RTT and delay jitter due to its simplicity, and offers easy migration from the existing Internet.

In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed for energy harvesting applications. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the kick-up input voltage of the boost converter is reduced to 0.18 V. To verify the circuit characteristics, the conventional zero body bias charge pump and the proposed forward body bias charge pump were fabricated with 65 nm CMOS process. The measured output current of the proposed charge pump under 0.18-V input voltage is increased by 170% comparing to the conventional one at the output voltage of 0.5 V. In addition, the boost converter successfully boosts the 0.18-V input to higher than 0.65-V output.

Mobile Ad Hoc Networks (MANETs) offer quick and easy network deployment in situations where it is not possible otherwise and they can be used to provide mobile users with a temporary infrastructure to use services in the absence of fixed infrastructure. Nodes in MANETs are free to move and organize themselves in an arbitrary fashion. The challenging task in such dynamic environments is how to improve the service availability. Replicating a service at some nodes distributed across the network is an effective strategy. However, service replication can considerably impact the system energy consumption. Since mobile devices have limited battery resources, a dynamic and efficient service replication is necessary to support such environments. In this paper, we propose a distributed service replication scheme for achieving high service availability with reasonable energy consumption for MANETs. The proposed method called HDAR (Highly Distributed Adaptive Service Replication) divides the whole network into disjoint zones of at most 2-hops in diameter and builds a dynamic replication mechanism which selects new replica zones depending on their service demand and the tradeoff between the communication and replication energy consumption costs. Through simulations, we confirmed that our approach can achieve higher service availability with reasonable energy consumption than existing methods.

This letter mainly deals with the multi-rank signal detecting problem against Spherically Invariant Random Vector (SIRV) background with Invariance theory. It is proved that generalized likelihood ratio test (GLRT), Rao test and Wald test are all the Uniformly Most Powerful Invariant (UMPI) detectors in SIRV distributions under a mild technical condition.

In this paper, we propose two authenticated key exchange(AKE) protocols and prove their security in the extended Canetti-Krawczyk model. The first protocol, called NAXOS+, is obtained by slightly modifying the NAXOS protocol proposed by LaMacchia, Lauter and Mityagin [15]. We prove its security under the Computational Diffie-Hellman (CDH) assumption by using the trapdoor test introduced in [6]. To the authors' knowledge, this is the first AKE protocol which is secure under the CDH assumption in the eCK model. The second protocol, called NETS, enjoys a simple and tight security reduction compared to existing schemes including HMQV and CMQV without using the Forking Lemma. Since each session of the NETS protocol requires only three exponentiations per party, its efficiency is also comparable to MQV, HMQV and CMQV.

The traditional mobile consumer electronics such as media players and smart phones use two distinct memories, SDRAM and Flash memory. SDRAM is used as main memory since it has characteristic of byte-unit random accessibility while Flash memory as secondary storage due to its characteristic of non-volatility. However, the advent of Storage Class Memory (SCM) that supports both SDRAM and Flash memory characteristics gives an opportunity to design a new system configuration. In this paper, we explore four feasible system configurations, namely RAM-Flash, RAM-SCM, SCM-Flash and SCM-Only. Then, using a real embedded system equipped with FeRAM, a type of SCM, we analyze the tradeoffs between performance and energy efficiency of each configuration. Experimental results have shown that SCM has great potential to reduce energy consumption for all configurations while performance is highly application dependent and might be degraded on the SCM-Flash and SCM-Only configuration.

In this paper, we propose two new chosen-ciphertext (CCA) secure schemes from the computational Diffie-Hellman (CDH) and bilinear computational Diffie-Hellman (BCDH) assumptions. Our first scheme from the CDH assumption is constructed by extending Cash-Kiltz-Shoup scheme. This scheme yields the same ciphertext as that of Hanaoka-Kurosawa scheme (and thus Cramer-Shoup scheme) with cheaper computational cost for encryption. However, key size is still the same as that of Hanaoka-Kurosawa scheme. Our second scheme from the BCDH assumption is constructed by extending Boyen-Mei-Waters scheme. Though this scheme requires a stronger underlying assumption than the CDH assumption, it yields significantly shorter key size for both public and secret keys. Furthermore, ciphertext length of our second scheme is the same as that of the original Boyen-Mei-Waters scheme.

In this paper, we introduce the intermediate hashed Diffie-Hellman (IHDH) assumption which is weaker than the hashed DH (HDH) assumption (and thus the decisional DH assumption), and is stronger than the computational DH assumption. We then present two public key encryption schemes with short ciphertexts which are both chosen-ciphertext secure under this assumption. The short-message scheme has smaller size of ciphertexts than Kurosawa-Desmedt (KD) scheme, and the long-message scheme is a KD-size scheme (with arbitrary plaintext length) which is based on a weaker assumption than the HDH assumption.

In this letter, we discuss a forwarding method for maximizing network lifetime, which combines multi-hop forwarding and direct forwarding with a direct/multi-hop forwarding ratio of each sensor node. The direct forwarding ratio refers to the forwarding amount ratio of sensor nodes' own data directly towards a sink node in one packet/instance data generation rate. We tackle an optimization problem to determine the direct forwarding ratio of each sensor node, maximizing network lifetime, as well as nearly guaranteeing energy consumption balancing characteristics. The optimization problem is tackled through the Lagrange multiplier approach. We found that the direct forwarding ratio is overall inversely proportional to the increase of node index in h < i ≤ N case. Finally, we compare energy consumption and network lifetime of the proposed forwarding method with other existing forwarding methods. The numerical results show that the proposed forwarding method balances energy consumption in most of the sensor nodes, comparing with other existing forwarding methods, such as multi-hop forwarding and direct forwarding. The proposed forwarding method also maximizes network lifetime.

In-network data aggregation is one of the most important issues for achieving energy-efficiency in wireless sensor networks since sensor nodes in the surrounding region of an event may generate redundant sensed data. The redundant sensed data should be aggregated before being delivered to the sink to reduce energy consumption. Which node should be selected as a Data Aggregation Node (DAN) for achieving the best energy efficiency is a difficult issue. To address this issue, this letter proposes a scheme to select a DAN for achieving energy-efficiency in an event region. The proposed scheme uses an analytical model to select the sensor node that has the lowest total energy consumption for gathering data from sensor nodes and for forwarding aggregated data to a sink, as a DAN. Analysis and simulation results show that the proposed scheme is superior to other schemes.

An assume-guarantee verification method has been recognized as a promising approach to verify component-based software by model checking. This method is not only fitted to component-based software but also has a potential to solve the state space explosion problem in model checking. The method allows us to decompose a verification target into components so that we can model check each of them separately. In this method, assumptions are seen as the environments needed for the components to satisfy a property and for the rest of the system to be satisfied. The number of states of the assumptions should be minimized because the computational cost of model checking is influenced by that number. Thus, we propose a method for generating minimal assumptions for the assume-guarantee verification of component-based software. The key idea of this method is finding the minimal assumptions in the search spaces of the candidate assumptions. The minimal assumptions generated by the proposed method can be used to recheck the whole system at much lower computational cost. We have implemented a tool for generating the minimal assumptions. Experimental results are also presented and discussed.