A novel voltage level controller for low-power charge pump converters will be presented in this paper. The proposed voltage level controller would react according to the pumped voltage in the charge-transfer-switch (CTS) converter. For the CTS circuit, the pumping operation would be degraded by the charge sharing effect in the auxiliary switch path. In this study, a voltage shifter was used as the voltage level controller to overcome this serious problem without consuming too much chip area. The simulation results showed that the converter can accept a rated input of 1.5 V and generated an output up to 8 V based on the TSMC 0.35-µm CMOS technology. The layout consumed an area of 125*160 µm2. The highest output obtained in measuring the real chip was 5.5 V which is primarily due to the limitation that the transistor could tolerated. The largest load was estimated as high as 6 mW which is large enough for on-chip application.

In real-time data-dominated communication and multimedia processing applications, a multi-layer memory hierarchy is typically used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller on-chip memories rather than from large background memories. This paper focuses on the reduction of the dynamic energy consumption in the memory subsystem of multidimensional signal processing systems, starting from the high-level algorithmic specification of the application. The paper presents a formal model which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings of dynamic energy from 40% to over 70% relative to the energy used in the case of flat memory designs.

Current distribution on a 2-layer PCB with lumped circuits is estimated by measuring the near electric field. In this method, the current estimation model is made without considering the electrical parameters of lumped circuits. Experimental results are demonstrated and compared with the numerical results, confirming the validity of this method.

To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm10.5 µm. The power consumption of the ILO is 9.6 µW at 250 MHz, 255 µW at 2.4 GHz and 1.47 mW at 4.8 GHz. The phase noise is -105 dBc/Hz at a 1 MHz offset.

Three miniaturized lumped-element power dividers with a filtering function for use in quadrature mixers are described. Simulation results showed that they can be miniaturized, as compared to conventional ones with open/short stubs, while maintaining the filter characteristics. A fabricated 0.95-GHz 0power divider with a filtering function had a chip size about half that of a conventional lumped-element one. Its insertion loss at 0.950.05 GHz was 4.00.1 dB.

In real-time embedded systems, there is requirement for adapting both energy consumption and Quality of Services (QoS) of tasks according to their importance. This paper proposes an adaptive power-aware resource allocation method to resolve a trade-off between the energy consumption and QoS levels according to their importance with guaranteeing fairness. The proposed resource allocator consists of two components: the total resource optimizer to search for the optimal total resource and QoS-fairness-based allocator to allocate resource to tasks guaranteeing the fairness. These components adaptively achieve the optimal resource allocation formulated by a nonlinear optimization problem with the time complexity O(n) for the number of tasks n even if tasks' characteristics cannot be identified precisely. The simulation result shows that the rapidness of the convergence of the resource allocation to the optimal one is suitable for real-time systems with large number of tasks.

A useful optimization problem to help solve various base station layout problems in multihop wireless networks is formulated. By solving the proposed generalized formula, the relation between the permissible largest number of hops and the minimum base station density necessary to cover an entire service area while guaranteeing a specified QoS is easily calculated. Our formula is extendable to other allocation problems by replacing parameters. The energy-cost transformation and scope of the multihop effect are also presented.

A cross-coupled charge pump with internal pumping capacitor, which is advantageous from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using NMOS and PMOS diodes connected to boosting nodes from VIN nodes, the pumping node is precharged to the same value at the pumping node in starting pumping. Since the first-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located in front of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with the conventional cross-coupled charge pump by using a stack-MIM capacitor. A proposed charge pump for TFT-LCD driver IC is designed with 0.13 µm triple-well DDI process, fabricated, and tested.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

Video surveillance systems have a huge market, as indicated by the number of installed cameras, particularly for low-power systems. In this paper, we propose a low-power quadtree video encoder for video surveillance systems. It features a low-complexity motion estimation algorithm, an application-specific ME-MC processor, a dedicated quadtree encoder engine and a processor control-based clock-gating technique. A chip capable of encoding 30 fps VGA (640480) at 80 MHz is fabricated using 0.18 µm CMOS technology. A total of 153 K gates with 558 kbits SRAM have been integrated into a 5.0 mm3.5 mm die. The power consumption is 40.87 mW at 80 MHz for VGA at 30 fps and 1.97 mW at 3.3 MHz for QCIF at 15 fps.

This paper proposes an efficient systolic array construction method for optimal planar systolic design of the matrix multiplication. By connection network adjustment among systolic array processing element (PE), the input/output data are jumping in the systolic array for multiplication operation requirements. Various 2-D systolic array topologies, such as square topology and hexagonal topology, have been studied to construct appropriate systolic array configuration and realize high performance matrix multiplication. Based on traditional Kung-Leiserson systolic architecture, the proposed "Jumping Systolic Array (JSA)" algorithm can increase the matrix multiplication speed with less processing elements and few data registers attachment. New systolic arrays, such as square jumping array, redundant dummy latency jumping hexagonal array, and compact parallel flow jumping hexagonal array, are also proposed to improve the concurrent system operation efficiency. Experimental results prove that the JSA algorithm can realize fully concurrent operation and dominate other systolic architectures in the specific systolic array system characteristics, such as band width, matrix complexity, or expansion capability.

This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.

A low-ripple diode charge-pump type AC-DC converter based on the Cockcroft-Walton diode multiplier is proposed for coil-coupled passive IC tags in this paper. This circuit is developed as a power supply for passive RFID tags with smart functions such as heart rate detection and/or body temperature measurement. The proposed circuit converts wirelessly induced power to a low-ripple DC voltage suitable for a 13.56 MHz RFID tag. The proposed circuit topology and the principle of operation are explained and treated theoretically by using quasi-equivalent small-signal models. The proposed circuit was implemented on a PCB. And it was confirmed that the proposed circuit provides 3.3 V DC with a ripple of less than 20 mV when a 4 Vp-p sinusoidal input is applied. Under this condition, the maximum output power is about 310 µW. The measured results were in good agreement with theoretical and HSPICE simulation results.

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9 VDD while the conventional one only 2 VDD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-µm and 40-V CMOS high-voltage process.

In this paper, we propose a novel network selection algorithm considering power consumption in hybrid wireless networks for vertical handover. CDMA, WiBro, WLAN networks are candidate networks for this selection algorithm. This algorithm is composed of the power consumption prediction algorithm and the final network selection algorithm. The power consumption prediction algorithm estimates the expected lifetime of the mobile station based on the current battery level, traffic class and power consumption for each network interface card of the mobile station. If the expected lifetime of the mobile station in a certain network is not long enough compared the handover delay, this particular network will be removed from the candidate network list, thereby preventing unnecessary handovers in the preprocessing procedure. On the other hand, the final network selection algorithm consists of AHP (Analytic Hierarchical Process) and GRA (Grey Relational Analysis). The global factors of the network selection structure are QoS, cost and lifetime. If user preference is lifetime, our selection algorithm selects the network that offers longest service duration due to low power consumption. Also, we conduct some simulations using the OPNET simulation tool. The simulation results show that the proposed algorithm provides longer lifetime in the hybrid wireless network environment.

This study presents a class of miniature parallel-coupled bandpass filters with good selectivity and stopband rejection. Capacitive terminations are introduced to the conventional anti-parallel coupled-lines, and lumped-element K-inverters are employed, to achieve both size reduction and spurious suppression. Additionally, the capacitive cross-coupling effect can be introduced to obtain three transmission zeros to enhance the selectivity. Suitable equivalent-circuit models, along with design formulae, are also established. Specifically, via design examples, this work demonstrates the feasibility of proposed filter structures in microstrip configuration. Compared to the conventional parallel-coupled filters, the proposed filters exhibit over 60% size reduction, improved selectivity, and wider stopbands up to four times the center frequency.

Previously Verifier-Local Revocation (VLR) group signature schemes from bilinear maps were proposed. In VLR schemes, only verifiers are involved in the revocation of a member, while signers are not. Thus, the VLR schemes are suitable for mobile environments. Furthermore, the previously proposed schemes satisfy the important backward unlinkability. This means that even after a member is revoked, signatures produced by the member before the revocation remain anonymous. This property is needed in case of a voluntary leave of a member or in case of a key loss. However, in the previous schemes, signatures become long, due to the adopted assumption, which should be improved in order to apply the schemes to the mobile environments. In this paper an improved VLR scheme is proposed with the shorter group signatures. This is achieved by using a different assumption, DLDH assumption, and improving zero-knowledge proofs in the group signatures. The length of the proposed group signatures is reduced to about 53% of that of the previous ones.

There are three well-known identification schemes: the Fiat-Shamir, GQ and Schnorr identification schemes. All of them are proven secure against the passive or active attacks under some number-theoretic assumptions. However, efficiencies of the reductions in those proofs of security are not tight, because they require "rewinding" a cheating prover. We show an identification scheme IDKEA1, which is an enhanced version of the Schnorr scheme. Although it needs the four exchanges of messages and slightly more exponentiations, the IDKEA1 is proved to be secure under the KEA1 and DLA assumptions with tight reduction. The idea underlying the IDKEA1 is to use an extractable commitment for prover's commitment. In the proof of security, the simulator can open the commitment in two different ways: one by the non-black-box extractor of the KEA1 assumption and the other through the simulated transcript. This means that we don't need to rewind a cheating prover and can prove the security without loss of the efficiency of reduction.

Non-malleability is an important security property of commitment schemes. The property means security against the man-in-the-middle attack, and it is defined and proved in the simulation paradigm using the corresponding simulator. Many known non-malleable commitment schemes have the common drawback that their corresponding simulators do not work in a straight-line manner, requires rewinding of the adversary. Due to this fact, such schemes are proved non-malleable only in the stand-alone cases. In the multiple-instances setting, i.e., when the scheme is performed concurrently with many instances of itself, such schemes cannot be proved non-malleable. The paper shows an efficient commitment scheme proven to be non-malleable even in the multiple-instances setting, based on the KEA1 and DDH assumptions. Our scheme has a simulator that works in a straight-line manner by using the KEA1-extractor instead of the rewinding strategy.

The ESIGN signature scheme was initially proposed in 1985. Since then, several variants have been proposed, but only a few have been formally supported using the methodology of provable security. In addition, these schemes are different from the ESIGN-PSS signature scheme submitted to ISO/IEC-14888-2 for standardization. It is believed that ESIGN-PSS is secure against the chosen-message attack, however, there has not yet been any report verifying this belief. This paper presents the security proofs of ESIGN-PSS and a variant of this scheme, denoted ESIGN-PSS-R, which is a signature scheme comprising the ESIGN signature mechanism and the PSS-R mechanism.