We propose a new electric contact device for arc discharge suppression. The functions of conventional electric contacts are categorized into energizing switch contacts and transient current switch contacts. A capacitor is connected in series to a transient current switch. Suppression of power consumption and arc discharge at breaking contacts are proposed, experimentally measured, and theoretically analyzed. The transient V-I characteristics at breaking contacts are controlled by the transient current switch and the capacitor. The transient responses at contacts were numerically derived by SPICE, and the energizing switch contacts voltage could be controlled to less than the minimum arc voltage. Using 2 conventional relays, no arc ignition at breaking contacts was confirmed for 50 V/25 A.

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, low-pass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.

Novel gain monitoring scheme in Remotely-Pumped EDF/DRA hybrid inline amplifier is proposed using Optical Time Domain Reflectometer (OTDR). Signal degradation due to cross gain modulation (XGM) caused by an OTDR pulse in the distributed Raman amplifier (DRA) section and remotely-pumped EDF (RP-EDF) unit is analyzed theoretically. The required conditions for suppressing of XGM in the DRA section are derived. We propose the directional bypass configuration to realize OTDR measurement without XGM in the EDF unit. Transmission experiments using the RP-EDF/DRA hybrid inline amplifier demonstrate the absence of transmission impairement induced by OTDR. An analysis of the OTDR trace for each gain medium is also discussed. The theoretical analysis agrees well with the experimental result.

This paper proposes a group signature scheme with efficient membership revocation. Though group signature schemes with efficient membership revocation based on a dynamic accumulator were proposed, the previous schemes force a member to change his secret key whenever he makes a signature. Furthermore, for the modification, the member has to obtain a public membership information of O(nN) bits, where n is the length of the RSA modulus and N is the total number of joining members and removed members. In our scheme, the signer needs no modification of his secret, and the public membership information has only K bits, where K is the maximal number of members. Then, for middle-scale groups with the size that is comparable to the RSA modulus size (e.g., up to about 1000 members for 1024 bit RSA modulus), the public membership information is a single small value only, while the signing/verification also remains efficient.

To avoid over-engineered and expensive systems, it is important that the design takes account of variations in optical fiber characteristics due to the presence of many fiber pieces and splices in optical fiber networks. We present a design method for optical fiber networks that employ distributed Raman amplification (DRA), that considers variations in both optical losses at signal and pump wavelengths, Raman gain characteristics and splice losses. Our method can be applied to the design of both newly developed systems and installed systems. We show design examples based on our method and reveal the practicability of our method.

This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics. In the future, it is predicted that operating frequency will rapidly increase and supply voltage will dramatically decrease. Besides, rigid noise performances will be required. In this condition, it is not clear neither how performances of both PLLs will change nor the performance differences between both PLLs will change. This paper predicts and compares future performances of PLLs using a RingVCO and an LCVCO with a qualitative evaluation by an analytical approach and with design experiments based on predicted process parameters. Our discussion reveals that the relative performance difference between both PLLs will be unchanged. As technology advances, power dissipation and chip area of both PLLs favorably decrease, while, noise characteristics of both PLLs degrade, which indicates low noise PLL circuit design will be more important.

This paper discusses real-time language recognition by 1-dimensional one-way cellular automata (OCAs) and two-way cellular automata (CAs), focusing on limitations of the parallel computation power. To clarify the limitations, we investigate real-time recognition of cyclic strings of the form uk with u {0,1}+ and k 2. We show a version of pumping lemma for recognizing cyclic strings by OCAs, which can be used for proving that several languages are not recognizable by OCAs in real time. The paper also discusses the real-time language recognition of CAs by prefix and postfix computation, in which every prefix or postfix of an input string is also accepted, if the prefix or postfix is in the language. It is shown that there are languages L Σ+ such that L is not recognizable by OCA in real-time and the reversal of L and the concatenation LΣ* are recognizable by CA in real-time.

Test data volume and power consumption for scan-based designs are two major concerns in system-on-a-chip testing. However, test set compaction by filling the don't-cares will invariably increase the scan-in power dissipation for scan testing, then the goals of test data reduction and low-power scan testing appear to be conflicted. Therefore, in this paper we present a selective scan chain reconfiguration method for test data compression and scan-in power reduction. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. After the scan chain reconfiguration a dictionary is built to indicate the run-length of each compatible class and only the scan-in data for each class should be transferred from the ATE to the CUT so as to reduce test data volume. Experimental results for the larger ISCAS'89 benchmarks show that the proposed approach overcomes the limitations of traditional run-length coding techniques, and leads to highly reduced test data volume with significant power savings during scan testing in all cases.

The effects of air-intake format of forced-air-cooled equipment on the efficiency of air conditioning systems are studied. A modern data center features a large number of information-processing devices to provide telecommunication services. These devices generate considerable heat, and the equipment that houses these devices often employs "forced air cooling" in which a cooling effect is achieved by sucking in large amounts of room air. An air conditioning system used for a machine room filled with such equipment therefore requires high fan driving power resulting in significantly low air conditioning efficiency. In this study, we first performed mockup-based experiments to obtain a quantitative understanding of how different air-intake formats for equipment affect the temperature at various room locations such as equipment intake. We then created a model for predicting the temperature at various locations, and on the basis of this model, we analyzed the factors affecting intake temperature and examined how intake temperature affects air conditioning efficiency. It was found that placing air inlets in the lower 1/3 portion of forced-air-cooled equipment could prevent the equipment from reabsorbing the hot air that it blows out and therefore improve air conditioning efficiency.

First we introduce the high-frequency equivalent circuit model of the Fine Pitched Ball Grid Array (FPBGA) bonding for frequencies up to 20 GHz. The lumped circuit model of the FPBGA bonding was extracted based on S-parameters measurement and subsequent fitting of the model parameters. The test packages, which contain probing pads, coplanar waveguides and FPBGA ball bonding, were fabricated and measured. The suggested π-model of the FPBGA bonding consists of self-inductor, self-capacitor, and self-resistor components. From the extracted model, a solder ball of 350 µm diameter and 800 µm ball pitch has less than 0.08 nH self-inductance, 0.40 pF self capacitance, and about 10 mΩ self-resistance. In addition, the mutual capacitance caused by the presence of the adjacent bonding balls is included in the model. The FPBGA solder ball bonding has less than 1.5 dB insertion loss up to 20 GHz, and it causes negligible delay time in digital signal transmission. The extracted circuit model of FPBGA bonding is useful in design and performance simulation of advanced packages, which use FPBGA bonding.

A new CMOS positive charge pump (NCP-1) is proposed and compared with the conventional pump in this paper. The comparison indicates that this NCP-1 scheme delivers 1.6 times larger output current into the load with roughly 10% area penalty than the conventional pump. To alleviate the area overhead of NCP-1, another new NCP-2 is proposed, where its current drivability is slightly lower than NCP-1 by as small as 5% but it achieves much smaller layout penalty as small as 2-3% compared with the conventional pump. The effectiveness of NCP-1 is verified experimentally in this paper by using 0.35-µm n-well process technology. These NCP-1 and NCP-2 are useful to DRAMs and NOR-type flash memories with sub-1-V VDD, where their large-output-current nature is favorable.

Optimistic log-based rollback recovery protocols have been regarded as an attractive fault-tolerant solution in distributed systems based on message-passing paradigm due to low overhead in failure-free time. These protocols are based on a Piecewise Deterministic (PWD) Assumption model. They, however, assumed that all logged non-deterministic events in a consistent global recovery line must be determinately replayed in recovery time. In this paper, we give the impossibility of deterministic replaying of logged non-deterministic event in a consistent global recovery line as a Ω Line Problem, because of asynchronous properties of distributed systems: no bound on the relative speeds of processes, no bound on message transmission delays and no global time source. In addition, we propose a new optimistic log-based rollback recovery protocol, which guarantees the deterministic replaying of all logged non-deterministic events belonged in a consistent global recovery line and solves a Ω Line Problem in recovery time.

Cryptography and Coding Theory are closely related in many respects. Recently, the problem of "decoding Reed Solomon codes" (also known as "polynomial reconstruction") was suggested as an intractability assumption to base the security of protocols on. This has initiated a line of cryptographic research exploiting the rich algebraic structure of the problem and its variants. In this paper we give a short overview of the recent works in this area as well as list directions and open problems in Polynomial Reconstruction Based Cryptography.

The high-end telecom terminal and PDAs, sometimes called Personal Trusted Devices (PTDs) are programmable, have tens of megabytes memory, and rather fast processors. In this paper we analyze, when it is energy-efficient to transfer application data compressed over the downlink and then decompress it at the terminal, or compress it first at the terminal and then send it compressed over up-link. These questions are meaningful in the context of usual application code or data and streams that are stored before presentation and require lossless compression methods to be used. We deduce an analytical model and assess the model parameters based on experiments in 2G (GSM) and 3G (FOMA) network. The results indicate that if the reduction through compression in size of the file to be downloaded is higher than ten per cent, energy is saved as compared to receiving the file uncompressed. For the upload case even two percent reduction in size is enough for energy savings at the terminal with the current transmission speeds and observed energy parameters. If time is saved using compressed files during transmission, then energy is certainly saved. From energy savings at the terminal we cannot deduce time savings, however. Energy and time consumed at the server for compression/decompression is considered negligible in this context and ignored. The same holds for the base stations and other fixed telecom infrastructure components.

Recently, low-density parity-check (LDPC) codes have attracted much attention. LDPC codes can achieve the near Shannon limit performance like turbo codes. For the LDPC codes, the reduced complexity decoding algorithms referred to as uniformly most powerful (UMP) BP- and normalized BP-based algorithms were proposed for BPSK on an additive white Gaussian noise (AWGN) channel. The conventional BP and BP-based algorithms can be applied to BPSK modulation. For high bit-rate transmission, multilevel modulation is preferred. Thus, the BP algorithm for multilevel modulations is proposed in . In this paper, we propose the BP algorithm with reduced complexity for multilevel modulations, where the first likelihood of the proposed BP algorithm is modified to adjust multilevel modulations. We compare the error rate performance of the proposed algorithm with that of the conventional algorithm on AWGN and flat Rayleigh fading channels. We also propose the UMP BP- and normalized BP-based algorithms for multilevel modulations on AWGN and flat Rayleigh fading channels. We show that the error rate performance of the proposed BP algorithm is almost identical to that of the algorithm in, where the decoding complexity of the proposed BP algorithm is less than that of the algorithm in. We also show that the proposed BP-based algorithms can achieve the good trade-off between the complexity and the error rate performance.

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.

In this paper, a new full on-chip high efficiency DC-DC voltage up converter with no inductance element is presented with power efficiency more than 74%. A method in the charge pump is described to have a regulated 3.3 V from 1.5 V for output power 4 mW. For medium power class, 100-200 mW, a boost converter is designed with on-chip inductor for 1.5 V to 3.3 V conversion. A buck converter is also designed for 3.3 V to 1 V conversion with power efficiency 72%. Inductor property of bond-wire is employed in the on-chip inductors. Analysis of efficiency relations and simulation results are presented for 0.35 µm CMOS technology.

In this paper, we first show a multiple-use protocol under the Diffie-Hellman assumption such that the initialization phase is much more efficient than the previous one. We next present an efficient multiple-use protocol whose security is equivalent to breaking RSA. The securities of our protocols are all formally proved.

This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-pump circuit has been designed and simulated by using the TSMC 0.35 µm 1P4M CMOS technology. Simulation results show the feasibility of proposed structure for low-voltage high-frequency applications.