This paper presents a low-power implementation scheme of interpolation FIR filters using distributed arithmetic (DA). The key idea of the proposed scheme involves look-up tables generating only nonnegative values. Thus, the proposed scheme can minimize the dynamic power consumption of interpolation FIR filters using DA without additional hardware. When used for implementing a pulse shaping filter for CDMA2000 mobile stations, the proposed filter not only has almost the same hardware complexity as the conventional one; it also has approximately 43% reduced power consumption.

In this paper, we construct a new signature scheme which is provably secure against adaptive chosen message attack in the standard model under the strong RSA assumption. The proposed scheme is different from Cramer-Shoup scheme and Camenisch-Lysyanskaya scheme and is more efficient than them. The tradeoff of the proposed scheme is a slight increase of the secret key.

A distributor of digital contents desires to collect users' attributes. On the other hand, the users do not desire to offer the attributes owing to the privacy protection. Previously, an anonymous survey system for attributes statistics is proposed. In this system, asking trusted third parties' helps, a distributor can obtain the correct statistics of users' attributes, such as gender and age, while no information beyond the statistics is revealed. However, the system suffers from the inefficiency of a protocol to generate the statistics, since the cost depends on the number of all the users registering this survey system. This paper proposes an anonymous survey system, where this cost is independent from the number of all the registering users. In this accomplishment, a group signature scheme with attribute tracing is also proposed. A conventional group signature scheme allows a group member to anonymously sign a message on behalf of the group, while only a designated party can identify the signer. The proposed scheme further enables the party to trace signer's attribute.

The strong RSA assumption is an assumption that the following problem is hard to solve: Given an RSA modulus and a ciphertext, find a pair of plaintext and exponent corresponding to them. It differs from the standard RSA assumption in a sense that in the strong version, no exponent is given as an input. The strong RSA assumption is considered to be stronger than the RSA assumption, but their exact relationship is not known. We investigate the strength of the strong RSA assumption and show that the strong RSA assumption restricted to low exponents is equivalent to the assumption that RSA problem is intractable for any low exponent. We also show that in terms of algebraic computation, the strong RSA assumption is properly stronger than the RSA assumption if there exists an RSA modulus n such that gcd((n),3)=1 and RSA problem is intractable.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

In the FDTD simulation of microwave circuits, a device in very small size compared with the wavelength is often handled as a lumped element, but it may still occupy more than one cell instead of a wire structure without volume routinely employed in classical extended FDTD algorithms. In this paper, two modified extended FDTD algorithms incorporating a lumped element occupying more than one cell are developed directly from the integral form of Maxwell's equations based on the assumption whether displacement current exists inside the region where a device is present. If the displacement current exists, the modified extended FDTD algorithm can be represented as a Norton equivalent current-source circuit, or otherwise as a Thevenin equivalent voltage-source circuit. These algorithms are applied in the microwave line loaded by a lumped resistor and an active antenna to illustrated the efficiency and difference of the two algorithms.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

Frequency modulation (FM) noise spectroscopy with diode laser is applied to high-resolution Doppler-free spectroscopy of Cs atomic vapor near a dielectric surface with evanescent-wave pump-probe configuration. Both high resolution and high sensitivity are realized by using an extremely simple experimental setup, in which no sweep or precise tuning of laser frequency are required. Several experimental configurations of optical near-field spectroscopy are demonstrated, which is useful for an extensive study of resonant interactions of atoms and microscopic electronic systems in optical near-fields.

This paper presents circuit models for the description of the frequency-dependent behavior of coils for horizontal deflection in CRTs. This enables CRT circuit designers to use circuit simulation programs to predict the high-frequency behavior of the interaction between the deflection coils and the drive circuit. An overview is given of the major phenomena that occur in CRT deflection coils at various frequencies. Models are presented for the dissipative, the capacitive, and the resonant behavior in successive frequency intervals. With these models, phenomena such as power dissipation and ringing can not only be related to design parameters, but can also be calculated from impedance characteristics which are relatively easy to measure.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.

An advanced center biased search algorithm for block motion estimation is proposed in this letter. It adopts an innovative center biased search strategy to get correct motion vector. The computational complexity is reduced by strict application of the unimodal error surface assumption and half stop technique. Experimental results show that proposed algorithm has improved performance as compared to the conventional block matching algorithms.

A charge pump circuit suitable for positive high voltage generators at sub-1.5 V range is presented. The proposed heap-pump circuit provides a high voltage generator having not only high pumping efficiency by eliminating threshold voltage drop but also simplest single phase clock scheme.

A design method is proposed that yields the optimum remote pre-amplifier (RPRA) parameters considering cable repair, the results of include increased cable loss and insertion position uncertainty. The optimum RPRA location is given by the intersection point of optical SNR (OSNR) vs. RPRA location curves in two cases; the total cable repair loss is assumed to be inserted at the transmitter end and at the receiver end. This RPRA parameter gives the maximum OSNR in the worst loss insertion case by cable repair.

In this paper, we address the key enabling technologies for long-span WDM transmissions at 40 Gbit/s. Experimental results of 1.28 Tbit/s (32 40 Gbit/s) unrepeatered transmission over 240 km of conventional 80-µm2 NDSF will be reported. Bi-directional pumped distributed Raman amplification has allowed a record unrepeatered WDM transmission distance over this fibre type, without using effective-area-enlarged fibres or remotely pumped EDFAs.

To overcome the problems of the modified Dickson pump like NCP-2, another pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this letter for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this letter that CCTS-1 has lower gate-oxide stress, improved voltage pumping gain, and better power efficiency than NCP-2 so that CCTS-1 can be more suitable for multi-stage pump in particular at low VCC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.

In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

The effect of Unbalanced-Magnetic-Pull (UMP) on vibration and run-outs has become stringent in the design for high performance HDD spindle motors. In this paper, reducing the UMP and also minimizing its variability for an 8-pole 9-slot spindle motor to achieve robustness in the performance is described and illustrated using novel robust design methods. A screening experiment identifies the key design parameters. Using Design of experiment (DOE) and Analysis of Variance (ANOVA), the parameter design reduces the amplitude of UMP and minimizes its variability by product parameter optimization. The tolerance design improves the quality by tightening tolerances on product or process parameters to reduce the performance variation. The optimal design process includes considerations of manufacturing and process noises, such as manufacturing tolerances for the slot opening and variation of the rotor magnet magnetization distribution due to the magnetization fixture and process. The optimal design procedure is briefly introduced and the results are presented.