In-network data aggregation is one of the most important issues for achieving energy-efficiency in wireless sensor networks since sensor nodes in the surrounding region of an event may generate redundant sensed data. The redundant sensed data should be aggregated before being delivered to the sink to reduce energy consumption. Which node should be selected as a Data Aggregation Node (DAN) for achieving the best energy efficiency is a difficult issue. To address this issue, this letter proposes a scheme to select a DAN for achieving energy-efficiency in an event region. The proposed scheme uses an analytical model to select the sensor node that has the lowest total energy consumption for gathering data from sensor nodes and for forwarding aggregated data to a sink, as a DAN. Analysis and simulation results show that the proposed scheme is superior to other schemes.

An assume-guarantee verification method has been recognized as a promising approach to verify component-based software by model checking. This method is not only fitted to component-based software but also has a potential to solve the state space explosion problem in model checking. The method allows us to decompose a verification target into components so that we can model check each of them separately. In this method, assumptions are seen as the environments needed for the components to satisfy a property and for the rest of the system to be satisfied. The number of states of the assumptions should be minimized because the computational cost of model checking is influenced by that number. Thus, we propose a method for generating minimal assumptions for the assume-guarantee verification of component-based software. The key idea of this method is finding the minimal assumptions in the search spaces of the candidate assumptions. The minimal assumptions generated by the proposed method can be used to recheck the whole system at much lower computational cost. We have implemented a tool for generating the minimal assumptions. Experimental results are also presented and discussed.

Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this paper, we introduce Suspect Window to cover the clock cycle in which the bug is triggered. Then, we present an efficient approach to determine the suspect window. Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially. Since scan dumps are only taken in the suspect window with the proposed mechanism, the time required for locating the bug is greatly reduced. The approaches are evaluated using ISCAS'89 and ITC'99 benchmark circuits. The experimental results show that the proposed mechanism can significantly reduce the overall debug time compared to scan-based debug mechanism while keeping high observability.

Network life time and hence device life time is one of the fundamental metrics in wireless body area networks (WBAN). To prolong it, especially those of implanted sensors, each node must conserve its energy as much as possible. While a variety of wake-up/sleep mechanisms have been proposed, the wake-up radio potentially serves as a vehicle to introduce vulnerabilities and attacks to WBAN, eventually resulting in its malfunctions. In this paper, we propose a novel secure wake-up scheme, in which a wake-up authentication code (WAC) is employed to ensure that a BAN Node (BN) is woken up by the correct BAN Network Controller (BNC) rather than unintended users or malicious attackers. The scheme is thus particularly implemented by a two-radio architecture. We show that our scheme provides higher security while consuming less energy than the existing schemes.

Density ratio estimation has gathered a great deal of attention recently since it can be used for various data processing tasks. In this paper, we consider three methods of density ratio estimation: (A) the numerator and denominator densities are separately estimated and then the ratio of the estimated densities is computed, (B) a logistic regression classifier discriminating denominator samples from numerator samples is learned and then the ratio of the posterior probabilities is computed, and (C) the density ratio function is directly modeled and learned by minimizing the empirical Kullback-Leibler divergence. We first prove that when the numerator and denominator densities are known to be members of the exponential family, (A) is better than (B) and (B) is better than (C). Then we show that once the model assumption is violated, (C) is better than (A) and (B). Thus in practical situations where no exact model is available, (C) would be the most promising approach to density ratio estimation.

In this letter, we propose an energy efficient hybrid architecture, the Hybrid MAC-based Robust Architecture (HMR), for wireless sensor networks focusing on MAC layer's scheduling and adaptive security suite as a security sub layer. A hybrid MAC layer with TDMA and CSMA scheduling is designed to prolong network life time, and the multi-channel TDMA based active/sleep scheduling is presented. We also present the security related functionalities needed to employ a flexible security suite to packets dynamically. Implementation and testbed of the proposed framework based on IEEE 802.15.4 are shown as well.

The usage of light-weight mobile devices is increasing rapidly, leading to demand for more telecommunication services. Consequently, mobile ad hoc networks and their applications have become feasible with the proliferation of light-weight mobile devices. Many protocols have been developed to handle service discovery and routing in ad hoc networks. However, the majority of them did not consider one critical aspect of this type of network, which is the limited of available energy in each node. Cluster Based Routing Protocol (CBRP) is a robust/scalable routing protocol for Mobile Ad hoc Networks (MANETs) and superior to existing protocols such as Ad hoc On-demand Distance Vector (AODV) in terms of throughput and overhead. Therefore, based on this strength, methods to increase the efficiency of energy usage are incorporated into CBRP in this work. In order to increase the stability (in term of life-time) of the network and to decrease the energy consumption of inter-cluster gateway nodes, an Enhanced Gateway Cluster Based Routing Protocol (EGCBRP) is proposed. Three methods have been introduced by EGCBRP as enhancements to the CBRP: improving the election of cluster Heads (CHs) in CBRP which is based on the maximum available energy level, implementing load balancing for inter-cluster traffic using multiple gateways, and implementing sleep state for gateway nodes to further save the energy. Furthermore, we propose an Energy Efficient Cluster Based Routing Protocol (EECBRP) which extends the EGCBRP sleep state concept into all idle member nodes, excluding the active nodes in all clusters. The experiment results show that the EGCBRP decreases the overall energy consumption of the gateway nodes up to 10% and the EECBRP reduces the energy consumption of the member nodes up to 60%, both of which in turn contribute to stabilizing the network.

Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250 nH to 320 nH is the best design feature that meets all requirements, including high output voltage above 20 V, fast rise time, low energy consumption, and area smaller than 25 mm2. The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.

Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects -- namely power consumption and chip area -- are heavily influenced, if not dominated, by the data access and storage aspects. This paper presents an energy-aware memory allocation methodology. Starting from the high-level behavioral specification of a given application, this framework performs the assignment of the multidimensional signals to the memory layers -- the on-chip scratch-pad memory and the off-chip main memory -- the goal being the reduction of the dynamic energy consumption in the memory subsystem. Based on the assignment results, the framework subsequently performs the mapping of signals into both memory layers such that the overall amount of data storage be reduced. This software system yields a complete allocation solution: the exact storage amount on each memory layer, the mapping functions that determine the exact locations for any array element (scalar signal) in the specification, and an estimation of the dynamic energy consumption in the memory subsystem.

A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.

In this paper, the vibration characteristics of stapes, driven by the implanted differential floating mass transducer (DFMT) in the human middle ear, are analyzed by using an electrical model. The electrical model has been simulated by using the PSpice, in which the simulated results are compared with the experimental results by using the fabricated DFMT and the human temporal bones.

In 1999, Gennaro, Halevi and Rabin proposed a signature which achieves provable security without assuming the random oracles, and it is the first RSA-type signature whose security is proved in the standard model. Since that time, several signatures have been proposed to achieve better efficiency or useful property along with the provable security in the standard model. In this paper, we construct a trapdoor hash function, and design an efficient online/offline signature by using the trapdoor hash function. Our signature scheme requires only one non-modular multiplication of two small integers for online signing, and it provides the fastest online signing among all online/offline signatures that achieve provable security in the standard model.

This letter presents the construction and design equations of a lumped element Wilkinson divider with dual-band operation. This divider is constructed of series and parallel LC resonant circuits, and an isolation resistor. The element values can be uniquely determined by giving the two frequencies for operation as a Wilkinson divider and the load resistance. An 800 MHz/2 GHz dual-band Wilkinson divider is treated as a design example, and its operation is verified by simulation and experiment. The fabricated divider has compact dimensions of 3.564 mm2.

Many DSP applications such as FIR filtering and DCT (discrete cosine transformation) require multiplication with constants. Therefore, optimizing the performance of constant multiplication improves the overall performance of these applications. It is well-known that shifting can replace a constant multiplication if the constant is a power of two. In this paper, we extend this idea in such a way that by employing more than two barrel shifters, we can design highly efficient constant multipliers. We have found that by using two or three shifters, we can generate a large set of constants. Using these constants, we can execute a typical set of FIR or DCT applications with few errors. Furthermore, with variable precision support, we can carry out a fairly large class of DSP applications with high computational efficiency. Compared to conventional multipliers, we can achieve power savings of up to 56% with negligible computational errors.

Accompanying with the popularization of portable equipments, and the rapid growth of the size of the electric systems, efficient low power design methodologies have been highly required. To satisfy these requests, a high accurate and high efficient power analysis in higher abstraction level is very important. The design environment is composed by efficient algorithms of power modeling, power library building, and data extracting. Those components of the environment should be balanced for the total efficiency and accuracy. We have proposed a new efficient power modeling environment which uses a look-up table (LUT). It reduces the size of the LUT drastically, compared to conventional algorithms. It makes the power analysis and library building high efficient. The experimental results show that our approach reduces the computation time to build the library to one tenth while keeping the accuracy of the power analysis. The RMS error and the largest error has been less than 8.30%, 59.16%, respectively.

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.

An AuSn reflow process using hydrogen radicals as a way to avert the cleaning of flux residues was investigated for its application to solder bumping. AuSn particles (manufactured by a gas atomizer) smaller than 5 µm, which are difficult to reflow by conventional methods that use rosin mildly activated (RMA) flux, were used for the experiments. In this process, the reduction effect by the hydrogen radicals removes the surface oxides of the AuSn particles. Excellent wetting between 1-µm-diameter AuSn particles and Ni metallization occurred in hydrogen plasma. Using hydrogen radicals, 100 µm-diameter AuSn bumps without voids were successfully formed at a peak temperature of 300. The average bump shear strength was approximately 73 gf/bump. Bump inspection after shear testing showed that a fracture had occurred between the Au/Ni/Cr under bump metallurgy (UBM) and Si substrate, suggesting sufficient wetting between the AuSn bump and the UBM.

Wireless sensor networks (WSNs) have attracted a significant amount of interest from many researchers because they have great potential as a means of obtaining information of various environments remotely. WSNs have a wide range of applications, such as natural environmental monitoring in forest regions and environmental control in office buildings. In WSNs, hundreds or thousands of micro-sensor nodes with such resource limitations as battery capacity, memory, CPU, and communication capacity are deployed without control in a region and used to monitor and gather sensor information of environments. Therefore, a scalable and efficient network control and/or data gathering scheme for saving energy consumption of each sensor node is needed to prolong WSN lifetime. In this paper, assuming that sensor nodes synchronize to intermittently communicate with each other only when they are active for realizing the long-term employment of WSNs, we propose a new synchronization scheme for gathering sensor information using chaotic pulse-coupled neural networks (CPCNN). We evaluate the proposed scheme using computer simulations and discuss its development potential. In simulation experiments, the proposed scheme is compared with a previous synchronization scheme based on a pulse-coupled oscillator model to verify its effectiveness.

A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.