We have developed the design procedure of multi-wavelength pumped Raman amplifiers, introducing superposition rule and account for pump-to-pump energy transfer. It is summarized with respect to the pumping wavelength and power allocation. The comparisons between simulated and experimental results are presented. Section 2 reviews the fundamentals of Raman amplifier. In this section, Raman gain spectra measured for different fibers are presented and the difference among the spectra is discussed. Section 3 describes the way to determine the pumping wavelength allocation by introducing superposition method. By means of this design method, some optimized design examples are presented, where the peak levels of Raman gain are fixed to 10 dB for the wavelength range from 1525 nm to 1615 nm (C- plus L-band) in all cases. From these results, it is confirmed that better gain flatness can be obtained by using the larger number of pumps. Section 4 explains how the pump-to-pump energy transfer changes the gain profile by experimental and simulated results. In this section, simulation modeling to perform precise numerical simulation is also presented. From the above discussion, the design procedure can be simplified: (1) one determines pump wavelengths with which a desired composite Raman gain can be obtained by adding in logarithmic scale individual Raman gain spectra shifted by the respective wavelength differences with adequate weight factors. And (2), one predicts how much power should be launched in order to realize the weight factors through precise numerical simulations. Section 5 verifies the superposition rule and the effect of pump-to-pump energy transfer by comparing a measured Raman gain with a superposed one. The agreement of two gain profiles shows that the multi-wavelength pumped Raman gain profile contains only the individual gain profiles created by the respective pump wavelengths. Section 6 concludes this paper.

We have developed the design procedure of multi-wavelength pumped Raman amplifiers, introducing superposition rule and account for pump-to-pump energy transfer. It is summarized with respect to the pumping wavelength and power allocation. The comparisons between simulated and experimental results are presented. Section 2 reviews the fundamentals of Raman amplifier. In this section, Raman gain spectra measured for different fibers are presented and the difference among the spectra is discussed. Section 3 describes the way to determine the pumping wavelength allocation by introducing superposition method. By means of this design method, some optimized design examples are presented, where the peak levels of Raman gain are fixed to 10 dB for the wavelength range from 1525 nm to 1615 nm (C- plus L-band) in all cases. From these results, it is confirmed that better gain flatness can be obtained by using the larger number of pumps. Section 4 explains how the pump-to-pump energy transfer changes the gain profile by experimental and simulated results. In this section, simulation modeling to perform precise numerical simulation is also presented. From the above discussion, the design procedure can be simplified: (1) one determines pump wavelengths with which a desired composite Raman gain can be obtained by adding in logarithmic scale individual Raman gain spectra shifted by the respective wavelength differences with adequate weight factors. And (2), one predicts how much power should be launched in order to realize the weight factors through precise numerical simulations. Section 5 verifies the superposition rule and the effect of pump-to-pump energy transfer by comparing a measured Raman gain with a superposed one. The agreement of two gain profiles shows that the multi-wavelength pumped Raman gain profile contains only the individual gain profiles created by the respective pump wavelengths. Section 6 concludes this paper.

Highly reliable and high power weakly index guided buried-stripe type 980 nm pump laser diodes developed for undersea applications are reviewed. The 10,000-hour large scale reliability tests of the first generation LD chips shows that 16.7 FIT for the random failure was confirmed at 10C with 60% confidence level at 120 mW output power. We also fabricated a FBG locked co-axial type module using a can-sealed LD with a two-lens system, which showed a stable FBG locked mode oscillation at 980 nm under the temperature range from 5C to 45C. The 5,000-hour heat cycle test of the modules reveals that the cumulative failure rate after 27 years at 10C is expected to be 0.023%. These first generation LD modules were employed in the transoceanic commercial systems such as Pacific Crossing-1 and the Japan-US cable system projects. We have also succeeded in developing the 980 nm LD for higher output operation with optimizing waveguide design. The 1000 µm long LD showed CW kink-free operation up to 545 mW optical output and a maximum output power of over 650 mW, which was limited by thermal rollover. In addition, a preliminary aging test at 350 mW optical output power at 50C has shown stable operation up to 2,300 h. We also confirmed 300 mW kink-free fiber output power with a co-axial type module with the improved coupling efficiency of approximately 78%. These figures are the highest reported operation levels for 980-nm co-axial type modules.

Highly reliable and high power weakly index guided buried-stripe type 980 nm pump laser diodes developed for undersea applications are reviewed. The 10,000-hour large scale reliability tests of the first generation LD chips shows that 16.7 FIT for the random failure was confirmed at 10C with 60% confidence level at 120 mW output power. We also fabricated a FBG locked co-axial type module using a can-sealed LD with a two-lens system, which showed a stable FBG locked mode oscillation at 980 nm under the temperature range from 5C to 45C. The 5,000-hour heat cycle test of the modules reveals that the cumulative failure rate after 27 years at 10C is expected to be 0.023%. These first generation LD modules were employed in the transoceanic commercial systems such as Pacific Crossing-1 and the Japan-US cable system projects. We have also succeeded in developing the 980 nm LD for higher output operation with optimizing waveguide design. The 1000 µm long LD showed CW kink-free operation up to 545 mW optical output and a maximum output power of over 650 mW, which was limited by thermal rollover. In addition, a preliminary aging test at 350 mW optical output power at 50C has shown stable operation up to 2,300 h. We also confirmed 300 mW kink-free fiber output power with a co-axial type module with the improved coupling efficiency of approximately 78%. These figures are the highest reported operation levels for 980-nm co-axial type modules.

A K-band MMIC subharmonically pumped mixer integrating local oscillator (LO) amplifier has been developed. For up-converter application, it is necessary to reduce the leakage of second harmonic component of LO frequency to RF port, which is generated by nonlinear operation of LO amplifier. A quasi-lumped short-circuited stub using microstrip structure has been successfully applied to the MMIC mixer to enhance 2fLO-suppression. We propose a new configuration of a quasi-lumped short-circuited stub, which reduces the influence of parasitic elements of via-holes. The developed MMIC has a one-stage LO amplifier and it has shown about 10 dB-improvement of 2fLO-suppression compared to conventional configuration using a quarter-wavelength short-circuited stub.

We have proposed and implemented a spread spectrum (SS) wireless switch using 2.4 GHz front-end AlN/Al2O3 surface acoustic wave (SAW) matched filter (MF). Since the SAW MF has radio frequency (RF) front-end operation, RF components are not needed in the received circuit. High impedance in the peripheral circuit using passive devices has been employed for low current consumption. The SS wireless switches have been designed with the power consumption of less than 100 µW by using the SAW MF. It is confirmed that implemented SS wireless switch has a long battery life of 10 years and communication range of 30 m.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

This paper examines similarities between the Decision Diffie-Hellman (DDH) assumption and the Quadratic Residuosity (QR) assumption. In addition, we show that many cryptographic protocols based on the QR assumption can be reconstructed using the DDH assumption.

New positive and negative bias voltage generators for TFT-LCD's drivers utilizing charge pump circuits are introduced. The generators can generate positive or negative voltages with various amplitude by simply changing the number of pumping stages. By using the circuit simulation program HSPICE, it is demonstrated that the introduced generators can provide enough positive or negative voltages for TFT-LCD's drivers.

This paper presents the effect of stress on device degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs) due to stud bumping. Stud bumping above the MOSFET region generates interface traps at the Si/SiO2 interface and results in the degradation of transconductance in N-channel MOSFETs. The interface traps are apparently eliminated by both nitrogen and hydrogen annealing. However, the hot-carrier immunity after hydrogen annealing is one order of magnitude stronger than that after nitrogen annealing. This effect is explained by the termination of dangling bonds with hydrogen atoms.

This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO. The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit. The designed VCO operates at a wide frequency range of 75.8 MHz-1 GHz with a good linearity. The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed. Simulation results show that a locking time of the proposed PLL is 3.5 µs at 1 GHz and the power dissipation is 92 mW.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

We report on the fabrication and operation of all-NbN single flux quantum (SFQ) circuits with resistively shunted NbN/AlN/NbN tunnel junctions fabricated on silicon substrates. The critical current varied by about 5% in 400 NbN/AlN/NbN junction arrays, where the junction area was 88 µm2. Critical current densities of the NbN/AlN/NbN tunnel junctions showed exponential dependence on the deposition time of the AlN barrier. By using the 12-nm-thick Cu film as shunted resistors, non-hysteretic current-voltage characteristics were achieved. From dc-SQUID measurements, the sheet inductance of our NbN stripline was estimated to be around 1.2 pH at 4.2 K. We designed and fabricated circuits consisting of dc/SFQ converters, Josephson transmission lines, and T flip-flop-based SFQ/dc converters. The circuits demonstrated correct operation with a bias margin of more than 15% at 4.2 K.

A 5-pole lumped element bandpass filter (BPF) of center frequency 264.05 MHz and fractional bandwidth (FBW) 0.76% is designed and fabricated using YBa2Cu3O7-d (YBCO) thin films deposited on both sides of a MgO substrate(40 mm 40 mm 0.5 mm). The return loss, minimum insertion loss and ripple were measured to be 20.0 dB, less than 0.1 dB and less than 0.1 dB at 70 K, respectively. These results verify both the compactness and low loss characteristics in the VHF band. The simulated frequency response, where the frequency dependences of inductance (L) and capacitance (C) elements and housing effect are taken into account, is in good agreement with the measured frequency response.

This paper presents two types of two-variable analog filters with maximally flat magnitude-squared attenuation response in the two-dimensional pass region. These are applied in order to obtain five types for the distribution of two-dimensional pass regions with respect to the design of microwave band pass filters consisting of a cascade of commensurate-line filter and lumped LC filter or a cascade of two commensurate-line filters in different propagation times.

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

This paper describes a new millimeter-wave hybrid integrated circuit (HIC) technology which applies a thin film multi-layered dielectric substrate and flip-chip bonding technology employing stud bump bonding (SBB). We have previously proposed and demonstrated a novel HIC structure, named millimeter-wave flip-chip IC, (MFIC), applying an excellent dielectric material of benzocyclobutene (BCB) thin film and flip-chip bonding. In this paper, an advanced thin film multi-layer process using non-photosensitive BCB was newly developed. Characteristics of the transmission lines and the built-in MIM capacitor within the multi-layered structure were discussed. Furthermore, stud bump bonding was newly adapted to the MFIC as a flip-chip method, and the millimeter-wave characteristics of the bumps were examined. Using these technologies, we demonstrate characteristics of a miniaturized 25 GHz down converter MFIC. Our newly proposed HIC structure enabled us to bring down chip size to less than 1/3 of our conventional structure. Finally, we discuss future possibilities for high performance multi-chip-modules (MCMs) using SBB technology as a further improved HIC for compact millimeter-wave radio equipment.

An emitter coupled logic (ECL) compatible low-power GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) for 10-Gb/s optical communication systems has been developed. In order to decrease the power consumption and to maximize the timing margin, we estimated the power consumption for direct-coupled FET logic (DCFL) and source-coupled FET logic (SCFL) circuits in terms of the D-type flip-flop (D-FF) operating speed and the duty-ratio variation. Based on the result, we used SCFL circuits in the clock-generating circuit and the circuits operating at 10 Gb/s, and we used DCFL circuits in the circuits operating below 5 Gb/s. These ICs, which are mounted on ceramic packages, operate at up to 10 Gb/s with power consumption of 1.2 W for the 8:1 MUX and 1.0 W for the 1:8 DEMUX. This is the lowest power consumption yet reported for 10-Gb/s 8:1 MUX and 1:8 DEMUX.

The additive noise response of a charge pump phase-locked loop in the synchronous mode of operation has been studied. In order to determine the tracking and noise performances of the loop, mean square values of tracking error and local oscillator phase jitter have been analytically obtained. Analytical results agree well with the simulation results obtained here and elsewhere. The analysis performed can be used in choosing different system parameters for optimum system operation.

An on-chip high voltage generator applicable to low voltage flash memory is introduced. Bootstrapped gate transfer switches of two parallel paths suppress the voltage loss due to threshold voltage drop of transfer transistors. The simulated results demonstrate that proposed circuit designed with NMOS transistors having 0.8 volt threshold voltage works like an ideal charge pump circuit near 1.0 volt range with enough current driving capability.