A regulated charge pump (CP) with an extended range of load current is presented. A power-efficient adaptive feedback controller is adopted. Verified by a 0.18µm CMOS technology with a power supply of 3.3V, the measured output voltage of the CP is regulated above 5V when the load current is varied from 2.5mA to 50mA. The measured power efficiency spans from 81.7% at lighter load to 75.2% when load current is 50mA. The measured output ripples are small and below 24mV.

This paper proposes an analytical, closed-form AC-DC voltage multiplier model and investigates the dependency of output current and input power on circuit and device parameters. The model uses no fitting parameters and a frequency term applicable to both multipliers using diodes and metal-oxide semiconductor field effect transistors (MOSFETs). Analysis enables circuit designers to estimate circuit parameters, such as the number of stages and capacitance per stages, and device parameters such as saturation current (in the case of diodes) or transconductance (in the case of MOSFETs). Comparisons of the proposed model with SPICE simulation results as well as other models are also provided for validation. In addition, design optimizations and the impact of AC power source impedance on output power are also investigated.

As the use of information technology is rapidly expanding, the power consumption of IT equipment is becoming an important social issue. As such, the power supply of IT equipment must provide various power saving measures through advanced features. A digitally controlled power supply is attractive for satisfying this requirement due to its flexibility and advanced management functionality. However, a digitally controlled power supply has issues with its transient response performance because the conversion time of the analog-digital converter and the time required for digital processing in the digital controller adversely affect the dynamic characteristics. The present paper introduces a new approach that can improve the transient response performance of the digital point-of-load (POL) power supplies of computer processors. The resulting power systems use feed-forward transient control, in addition to the general voltage regulation feedback control loop, to improve their dynamic characteristics. On the feed-forward control path, the processor workload information is supplied to the power supply controller from the processor. The power supply controller uses the workload information to predict the power load change and generates an auxiliary control to improve the transient response performance. As the processor workload information, the processor-integrated performance counter values are sent to the power supply controller via a hardware interface. The processor power consumption prediction equation is modeled using the moving average model, which uses performance counter values of several past steps. The prediction equation parameters are defined by multiple regression analysis using the measured CPU power consumption data and experimentally obtained performance counter information. The analysis reveals that the optimum parameters change with time during transient periods. The modeled equation well explains the processor power load change. The measured CPU power consumption profile is confirmed to be accurately replicated by the prediction for a period of 200ns. Using the power load change prediction model, circuit simulations of the feed-forward transient control are conducted. It is validated that the proposed approach improves power supply transient response under some practical server workloads.

The amount of seasonings used during food preparation is quite important information for modern people to enable them to cook delicious dishes as well as to take care for their health. In this paper, we propose a near real-time automated system for measuring and recording the amount of seasonings used during food preparation. Our proposed system is equipped with two devices: electronic scales and a camera. Seasoning bottles are basically placed on the electronic scales in the proposed system, and the scales continually measure the total weight of the bottles placed on them. When a chef uses a certain seasoning, he/she first picks up the bottle containing it from the scales, then adds the seasoning to a dish, and then returns the bottle to the scales. In this process, the chef's picking and returning actions are monitored by the camera. The consumed amount of each seasoning is calculated as the difference in weight between before and after it is used. We evaluated the performance of the proposed system with experiments in 301 trials in actual food preparation performed by seven participants. The results revealed that our system successfully measured the consumption of seasonings in 60.1% of all the trials.

Most research projects with respect to energy saving are trying to improve power efficiency and are using software to manage the power systems in the power on mode; but in our design, we modify the original Suspend to RAM mode-S3 state, which is the 3rd system state as defined by the ACPI specification, in order to reduce power consumption. We've redesigned the control circuit to save power while a PC is in the standby mode. First, we re-examine the entire circuit in the standby mode, and clarify which chip is used both to wake up the system and to turn off all unnecessary standby power previously used by the chips. Secondly, we redesign the power sequence and use an additional chip to control the system power supply, to allow a PC's normal system's operation to turn off the unnecessary power control chips. Third, in order to save power supply in the standby mode, we have simplified the multiple remote wake-up mechanism to control the remote boot device. The improvement shows that our design reduced power consumption to 0.21W from the original 0.56W while all the remote wake-up functions are disabled; and consumes 0.42W when using multiple remote wake-up functions. We implement the above modification from the legacy S3 state, and obtain lower power consumption. In order to distinguish the standby states, we name the modified S3 state as Deep S3 state.

Due to the depletion of the public IPv4 address pool, Internet service providers will not be able to supply their new customers with public IPv4 addresses in the near future. Either they give private IPv4 addresses and use carrier grade NAT (CGN) or they move towards IPv6 and provide NAT64 service to the IPv6 only clients who want to reach IPv4 only servers. In both cases they must use a stateful NAT/NAT64 solution. When dimensioning a NAT/NAT64 gateway, the port number consumption of the clients is a key factor as the port numbers are 16 bits long and a unique one has to be provided for every session (when using traditional type NAPT, which does not include the destination IP address and port number in the tuple for the identification of TCP sessions) and a single web client may use several hundred sessions and an equal number of port numbers according to literature. In this paper, we present a method for the estimation of the port number consumption of web browsing. The method is based on the port number consumption measurements of the most popular web sites and their combination using the number of the visitors of the web sites as weight factors. We propose the resulting curve as an approximation of a general profile of the average port number consumption of web browsers after the first click, but without taking into consideration the effect of the web users' browsing behavior. We also discuss the case of the extended NAPT, which can reuse the source port numbers towards different destination IP addresses and/or destination port numbers. We propose a formula and give measurement results for the extended NAPT gateways, too. We disclose the measurement method in detail and provide the measurement scripts in Linux, too.

As energy consumption of cache memories increases, an energy-efficient cache management mechanism is required. While a dynamic cache resizing mechanism is one promising approach to the energy reduction of microprocessors, one problem is that its effect is limited by the existence of dead-on-fill blocks, which are not used until their evictions from the cache memory. To solve this problem, this paper proposes a cache management policy named FLEXII, which can reduce the number of dead-on-fill blocks and help dynamic cache resizing mechanisms further reduce the energy consumption of the cache memories.

Optimizing embedded software is a problem having scientific and practical signification. Optimizing embedded software can be done in different phases of the software life cycle under different optimal conditions. Most studies of embedded software optimization are done in forward engineering and these studies have not given an overall model for the optimization problem of embedded software in both forward engineering and reverse engineering. Therefore, in this paper, we propose a new approach to embedded software optimization based on reverse engineering. First, we construct an overall model for the embedded software optimization in both forward engineering and reverse engineering and present a process of embedded software optimization in reverse engineering. The main idea of this approach is that decompiling executable code to source code, converting the source code to models and optimizing embedded software under different levels such as source code and model. Then, the optimal source code is recompiled. To develop this approach, we present two optimization techniques such as optimizing power consumption of assembly programs based on instruction schedule and optimizing performance based on alternating equivalent expressions.

Accuracy of a method for analyzing the interface defect properties; time-domain charge pumping method, is evaluated. The method monitors the charge pumping (CP) current in time domain, and thus we expect that it gives us a noble way to investigate the interface state properties. In this study, for the purpose of evaluating the accuracy of the method, the interface state density extracted from the time-domain data is compared with that measured using the conventional CP method. The results show that they are equal to each other for all measured devices with various defect densities, demonstrating that the time-domain CP method is sufficiently accurate for the defect density evaluation.

Satellite clusters have been satisfactorily implemented in a number of applications, such as positioning and sensor networks, with the purpose of improving communication system capabilities. However, because the use of clusters requires good management of the resources, those solutions imply new challenges for communication systems. This paper focuses on improving the data management between network elements by considering a network formed by satellite clusters. Satellite clusters work in cooperation to provide real-time and non-real-time services in different footprint areas. This study proposes the adjustable energy consumption access scheme (AECS) as one possible solution response to particular necessities of communication and at the same time, as a way of decreasing the system energy consumption. Energy consumption is a key issue that concerns green network operations and it is directly linked to the cooperation and coordination between network elements. On the other hand, we support the implementation of Optical Inter-Satellite Links (OISL) for communication between cluster elements. The analysis involves the study of energy consumption, transmission delay, specific link margins, bit error rate (BER) and QoS.

It is important to reduce the power consumption of complementary metal oxide semiconductor (CMOS) logic circuits, especially those used in mobile devices. A CMOS logic circuit consists of metal-oxide-semiconductor field-effect transistors (MOSFETs), which consume electrical power dynamically when they charge and discharge load capacitance that is connected to their output. Load capacitance mainly exists in wiring or buses, and transitions between logic 0 and logic 1 cause these charges and discharges. Many methods have been proposed to reduce these transitions. One novel method (called segmentation coding) has recently been proposed that reduces power consumption of CMOS buses carrying band-limited signals, such as audio data. It improves performance by employing dedicated encoders for the upper and lower bits of transmitted data, in which the transition characteristics of band-limited signals are utilized. However, it uses a conventional majority voting circuit in the encoder for lower bits, and the circuit uses many adders to count the number of 1s to calculate the Hamming distance between the transmitted data. This paper proposes segmentation coding with pseudo-majority voting. The proposed pseudo-majority voting circuit counts the number of 1s with fewer circuit resources than the conventional circuit by further utilizing the transition characteristics of band-limited signals. The effectiveness of the proposed method was demonstrated through computer simulations and experiments.

In this letter, we prove that the Kurosawa-Desmedt (KD) scheme [10], which belongs to the hybrid framework, is KDM-CCA secure w.r.t. an ensemble proposed by Qin et al. in [12] under the decisional Diffie-Hellman assumption. Since our proof does not rely on the random oracle model, we partially answer the question presented by Davies and Stam in [7], where they hope to achieve the KDM-CCA security for hybrid encryption scheme in the standard model (i.e. not random oracle model). Moreover, our result may also make sense in practice since KD-scheme is (almost) the most efficient CCA secure scheme.

Coarse-grained Reconfigurable Architecture (CGRA) is a promising mobile computing platform that provides both high performance and high energy efficiency. In an application, loop nests are usually mapped onto CGRA for further acceleration, so optimizing the mapping is an important goal for design of CGRAs. Moreover, obviously almost all of mobile devices are powered by batteries, how to reduce energy consumption also becomes one of primary concerns in using CGRAs. This paper makes three contributions: a) Proposing an energy consumption model for CGRA; b) Formulating loop nests mapping problem to minimize the battery charge loss; c) Extract an efficient heuristic algorithm called BPMap. Experiment results on most kernels of the benchmarks and real-life applications show that our methods can improve the performance of the kernels and lower the energy consumption.

We present a time-to-digital converter (TDC) achieving sub-picosecond resolution and high precision for all-digital phase-locked-loops (ADPLLs). The basic idea is using a charge pump to translate time interval into charge, and a successive-approximation-register-analog-to-digital converter (SAR-ADC) to quantize the charge. With this less complex configuration, high resolution, high precision, low power, and small area can be achieved all together. We analyzed the noise contribution from the charge pump and describe detailed design and implementation for sizing the capacitor and transistors, with the awareness of noise and linearity. The analysis demonstrates the proposed TDC capable of sub-picosecond resolution and high precision. Two prototype chips were fabricated in 65nm CMOS with 0.06mm2, and 0.018mm2 core areas, respectively. The achieved resolutions are 0.84ps and 0.80ps, in 8-bit and 10-bit range, respectively. The measured single-shot-precisions range from 0.22 to 0.6ps, and from 0.66 to 1.04ps, respectively, showing consistent trends with the analysis. Compared with state-of-the-arts, best performance balance has been achieved.

In elevator-group control, the average number of running cars should be finely adjusted by the dynamically controlling the number of running cars (DCNRC). Traffic demand in an office building varies throughout the day. In this paper, we propose a new energy-saving method for elevator-group control that adjusts the number of running cars according to the traffic demand, simulate the proposed energy-saving method under nearly real traffic demand conditions of an office building, and reduce the daily energy consumption to the target level after several days.

In this paper, we propose a novel energy-efficient sensor device management scheme called sensor device personalization (SDP) for the Internet of things (IoT) and wireless sensor networks (WSNs) based on the IEEE 802.15.4 unslotted carrier sense multiple access with collision avoidance (CSMA/CA). In the IoT and WSNs with the star topology, a coordinator device (CD), user devices (UDs), and sensor devices (SDs) compose a network, and the UDs such as smart phones and tablet PCs manage the SDs, which consist of various sensors and communication modules, e.g., smart fridge, robot cleaner, heating and cooling system, and so on, through the CD. Thus, the CD consumes a lot of energy to relay packets between the UDs and the SDs and also has a longer packet transmission delay. Therefore, in order to reduce the energy consumption and packet transmission delay, in the proposed SDP scheme, the UDs obtain a list of SD profiles (including SDs' address information) that the UDs want to manage from the CD, and then the UDs and the SDs directly exchange control messages using the addresses of the SDs. Through analytical models, we show that the proposed SDP scheme outperforms the conventional scheme in terms of normalized throughput, packet transmission delay, packet loss probability, and total energy consumption.

It is clarified that the SiN$_{mathrm{X}}$ film with a thickness of 1.7 nm, which was formed at the interface between the poly-Si source/drain and Al layer, suppresses the hump phenomenon of TFT with a channel length of 10, $mu $m. The mechanism of the hump suppression by this structure is discussed. It is thought that the fixed charge in the SiN$_{mathrm{X}}$ film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion.

Bandwidth aggregation (BAG) techniques have been researched for many years in an efforts to enhance throughput for multi-homed streaming service. However, despite of the considerable attention being devoted towards energy-efficient communications, the power efficiency for BAG has not been considered yet. To improve the power efficiency in multi-homed streaming service, this paper proposes Power Minimized Rate Allocation Scheme (PMRAS) with optimal rate allocation at each interface while guaranteeing an allowable packet loss rate. In developing PMRAS, we first formulate a power consumption model based on the network interface state (i.e. active and idle state). We adopt a Lagrangian algorithm to solve the convex optimization problem of power consumption. The performance results gained from a numerical analysis and simulations (NS-2) reveal that the proposed scheme offers superior performance over the existing rate allocation scheme for BAG with guaranteed required quality of service.

Wireless body area networks (WBANs) have to work with low power and long lifetime to satisfy human biological safety requirements in e-health; therefore extremely low energy consumption is significant for WBANs. IEEE 802.15.6 standard has been published for wearable and implanted applications which provide communication technology requirements in WBANs. In this paper, the cross-layering optimization methodology is used to minimize the network energy consumption. Both the priority strategy and sleep mechanism in IEEE802.15.6 are considered. Macroscopic sleep model based on WBAN traffic priority and microscopic sleep model based on MAC structure are proposed. Then the network energy consumption optimization problem is solved by Lagrange dual method, the master problem are vertically decomposed into two sub problems in MAC and transport layers which are dealt with gradient method. Finally, a solution including self-adaption sleep mechanism and node rate controlling is proposed. The results of this paper indicate that the algorithm converges quickly and reduces the network energy consumption remarkably.

This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6,Wh (58%) when compared with the conventional method.