This paper proposes a moving source localization method that combines TDOA, FDOA and doppler rate measurements. First, the observation equations are linearized by introducing nuisance variables and an initial solution of all the variables is acquired using the weighted least squares method. Then, the Taylor expression and gradient method is applied to eliminate the correlation between the elements in the initial solution and obtain the final estimation of the source position and velocity. The proposed method achieves CRLB derived using TDOA, FDOA and doppler rate and is much more accurate than the conventional TDOA/FDOA based method. In addition, it can avoid the rank-deficiency problem and is more robust than the conventional method. Simulations are conducted to examine the algorithm's performance and compare it with conventional TDOA/FDOA based method.

Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

We consider a problem as follows: Given unit weights arriving in an online manner with the total cardinality unknown, upon each arrival we decide where to place it on the unit circle in $mathbb{R}^{2}$. The objective is to set the center of mass of the placed weights as close to the origin as possible. We apply competitive analysis defining the competitive difference as a performance measure. We first present an optimal strategy for placing unit weights which achieves a competitive difference of $rac{1}{5}$. We next consider a variant in which the destination of each weight must be chosen from a set of positions that equally divide the unit circle. We give a simple strategy whose competitive difference is 0.35. Moreover, in the offline setting, several conditions for the center of mass to lie at the origin are derived.

Many methods have been proposed for measuring the structural similarity between two protein folds. However, it is difficult to select one best method from them for the classification task, as each method has its own strength and weakness. Intuitively, combining multiple methods is one solution to get the optimal classification results. In this paper, by generalizing the concept of the large margin nearest neighbor (LMNN), a method for combining multiple distance metrics from different types of protein structure comparison methods for protein fold classification task is proposed. While LMNN is limited to Mahalanobis-based distance metric learning from a set of feature vectors of training data, the proposed method learns an optimal combination of metrics from a set of distance metrics by minimizing the distances between intra-class data and enlarging the distances of different classes' data. The main advantage of the proposed method is the capability in finding an optimal weight coefficient for combination of many metrics, possibly including poor metrics, avoiding the difficulties in selecting which metrics to be included for the combination. The effectiveness of the proposed method is demonstrated on classification experiments using two public protein datasets, namely, Ding Dubchak dataset and ENZYMES dataset.

Time performance optimization and resource conflict resolution are two important challenges in multiple project management contexts. Compared with traditional project management, multi-project management usually suffers limited and insufficient resources, and a tight and urgent deadline to finish all concurrent projects. In this case, time performance optimization of the global project management is badly needed. To our best knowledge, existing work seldom pays attention to the formal modeling and analyzing of multi-project management in an effort to eliminate resource conflicts and optimizing the project execution time. This work proposes such a method based on PRT-Net, which is a Petri net-based formulism tailored for a kind of project constrained by resource and time. The detailed modeling approaches based on PRT-Net are first presented. Then, resource conflict detection method with corresponding algorithm is proposed. Next, the priority criteria including a key-activity priority strategy and a waiting-short priority strategy are presented to resolve resource conflicts. Finally, we show how to construct a conflict-free PRT-Net by designing resource conflict resolution controllers. By experiments, we prove that our proposed priority strategy can ensure the execution time of global multiple projects much shorter than those without using any strategies.

We consider a problem of the choice of price plans offered by a telecommunications company: a “pay-as-you-go” plan and a “flat-rate” plan. This problem is formulated as an online optimization problem extending the ski-rental problem, and analyzed using the competitive ratio. We give a lemma for easily calculating the competitive ratio. Based on the lemma, we derive a family of optimal strategies for a realistic class of instances.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.

In lossy image/video encoding, there is a compromise between the number of bits and the extent of distortion. Optimizing the allocation of bits to different sources, such as frames or blocks, can improve the encoding performance. In intra-frame encoding, due to the dependency among macro blocks (MBs) introduced by intra prediction, the optimization of bit allocation to the MBs usually has high complexity. So far, no practical optimal bit allocation methods for intra-frame encoding exist, and the commonly used method for intra-frame encoding is the fixed-QP method. We suggest that the QP selection inside an image/a frame can be optimized by aiming at the constant perceptual quality (CPQ). We proposed an iteration-based bit allocation scheme for H.264/AVC intra-frame encoding, in which all the local areas (which is defined by a group of MBs (GOMBs) in this paper) in the frame are encoded to have approximately the same perceptual quality. The SSIM index is used to measure the perceptual quality of the GOMBs. The experimental results show that the encoding performance on intra-frames can be improved greatly by the proposed method compared with the fixed-QP method. Furthermore, we show that the optimization on the intra-frame can bring benefits to the whole sequence encoding, since a better reference frame can improve the encoding of the subsequent frames. The proposed method has acceptable encoding complexity for offline applications.

Zero-shot learning refers to the object classification problem where no training samples are available for testing classes. For zero-shot learning, attribute transfer plays an important role in recognizing testing classes. One popular method is the indirect attribute prediction (IAP) model, which assumes that all attributes are independent and equally important for learning the zero-shot image classifier. However, a more practical assumption is that different attributes contribute unequally to the classifier learning. We therefore propose assigning different weights for the attributes based on the relevance probabilities between the attributes and the classes. We incorporate such weighed attributes to IAP and propose a relevance probability-based indirect attribute weighted prediction (RP-IAWP) model. Experiments on four popular attributed-based learning datasets show that, when compared with IAP and RFUA, the proposed RP-IAWP yields more accurate attribute prediction and zero-shot image classification.

In this paper, we propose an example-based single image super resolution (SR) method by l2 approximation with self-sampled image patches. Example-based super resolution methods can reconstruct high resolution image patches by a linear combination of atoms in an overcomplete dictionary. This reconstruction requires a pair of two dictionaries created by tremendous low and high resolution image pairs from the prepared image databases. In our method, we introduce the dictionary by random sampling patches from just an input image and eliminate its training process. This dictionary exploits the self-similarity of images and it will no more depend on external image sets, which consern the storage space or the accuracy of referred image sets. In addition, we modified the approximation of input image to an l2-norm minimization problem, instead of commonly used sparse approximation such as l1-norm regularization. The l2 approximation has an advantage of computational cost by only solving an inverse problem. Through some experiments, the proposed method drastically reduces the computational time for the SR, and it provides a comparable performance to the conventional example-based SR methods with an l1 approximation and dictionary training.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

In this paper, we propose an efficient regularized zero-forcing (RZF) precoding method that has lower hardware resource requirements and produces a shorter delay to the first transmitted symbol compared with truncated polynomial expansion (TPE) that is based on Neumann series in massive multiple-input multiple-output (MIMO) systems. The proposed precoding scheme, named matrix decomposition-polynomial expansion (MDPE), essentially applies a matrix decomposition algorithm based on polynomial expansion to significantly reduce full matrix multiplication computational complexity. Accordingly, it is suitable for real-time hardware implementations and high-mobility scenarios. Furthermore, the proposed method provides a simple expression that links the optimization coefficients to the ratio of BS/UTs antennas (β). This approach can speed-up the convergence to the matrix inverse by a matrix polynomial with small terms and further reduce computation costs. Simulation results show that the MDPE scheme can rapidly approximate the performance of the full precision RZF and optimal TPE algorithm, while adaptively selecting matrix polynomial terms in accordance with the different β and SNR situations. It thereby obtains a high average achievable rate of the UTs under power allocation.

In a world of continuously expanding amounts of data, retrieving interesting information from enormous data sets becomes more complex every day. Solutions for precomputing views on these big data sets mostly follow either an offline approach, which is slow but can take into account the entire data set, or a streaming approach, which is fast but only relies on the latest data entries. A hybrid solution was introduced through the Lambda architecture concept. It combines both offline and streaming approaches by analyzing data in a fast speed layer first, and in a slower batch layer later. However, this introduces a new synchronization challenge: once the data is analyzed by the batch layer, the corresponding information needs to be removed in the speed layer without introducing redundancy or loss of data. In this paper we propose a new approach to implement the Lambda architecture concept independent of the technologies used for offline and stream computing. A universal solution is provided to manage the complex synchronization introduced by the Lambda architecture and techniques to provide fault tolerance. The proposed solution is evaluated by means of detailed experimental results.

This paper presents a practical system which allows instructors to easily introduce 3D games utilizing smartphones in a classroom. The system consists of a PC server, a big screen and smartphone clients. The server provides 3D models, so no 3D authoring is needed when using this system. For an instructor, preparing slides of quiz-questions with the correct answers is all that is required when designing 3D games. According to a quiz specified by an instructor, this system constructs a corresponding 3D game scene. The answers students provide on their smartphones will be used to play this game. Everyone in the classroom can see this 3D game in real time on a big screen. The game illustrates how every student has reacted to a quiz. This system also introduces specialized queues for mobile interactions; a queue for commands from an instructor and a queue for data from students. The command queue has higher priority than the data queue; so that an instructor can control this system by sending commands with clicks on a smartphone. Previous studies have mostly provided specially designed teaching materials to instructors, often treating them as passive consultants. However, by using slides, already familiar to instructors, this system enables instructors to combine their own teaching materials with 3D games in the classroom. Moreover, 3D games are expected to further motivate students to actively participate in classroom activities. This system is evaluated in this paper.

Computer networks require sophisticated control mechanisms to realize fair resource allocation among users in conjunction with efficient resource usage. To successfully realize fair resource allocation in a network, someone should control the behavior of each user by considering fairness. To provide efficient resource utilization, someone should control the behavior of all users by considering efficiency. To realize both control goals with different granularities at the same time, a hierarchical network control mechanism that combines microscopic control (i.e., fairness control) and macroscopic control (i.e., efficiency control) is required. In previous works, Aida proposed the concept of chaos-based hierarchical network control. Next, as an application of the chaos-based concept, Aida designed a fundamental framework of hierarchical transmission rate control based on the chaos of coupled relaxation oscillators. To clarify the realization of the chaos-based concept, one should specify the chaos-based hierarchical transmission rate control in enough detail to work in an actual network, and confirm that it works as intended. In this study, we implement the chaos-based hierarchical transmission rate control in a popular network simulator, ns-2, and confirm its operation through our experimentation. Results verify that the chaos-based concept can be successfully realized in TCP/IP networks.

In this paper, we formulate an optimal stabilization problem of quantitative discrete event systems (DESs) under partial observation. A DES under partial observation is a system where its behaviors cannot be completely observed by a supervisor. In our framework, the supervisor observes not only masked events but also masked states. Our problem is then to synthesize a supervisor that drives the DES to a given target state with the minimum cost based on the detected sequences of masked events and states. We propose an algorithm for deciding the existence of an optimal stabilizing supervisor, and compute it if it exists.

In modern communication systems, it is a critical and challenging issue for existing carrier tracking techniques to achieve near-ideal carrier synchronization without the help of pilot signals in the case of symbol rate sampling and low signal-to-noise ratio (SNR). To overcome this issue, this paper proposes an effective carrier frequency and phase offset tracking scheme which has a robust confluent synchronization architecture whose main components are a digital frequency-locked loop (FLL), a digital phase-locked loop (PLL), a modified symbol hard decision block and some sampling rate conversion blocks. As received signals are sampled at symbol baud rate, this carrier tracking scheme is still able to obtain precise estimated values of carrier synchronization parameters under the condition of very low SNRs. The performance of the proposed carrier synchronization scheme is also evaluated by using Monte-Carlo method. Simulation results confirm the feasibility of this carrier tracking scheme and demonstrate that it ensures that both the rate-3/4 irregular low-density parity-code (LDPC) coded system and the military voice transmission system utilizing the direct sequence spread spectrum (DSSS) technique achieve satisfactory bit-error rate (BER) performance at correspondingly low SNRs.

A novel circularly and linearly polarized loop antenna is presented. A simple loop configuration, twisted like a cross shape, has achieved radiating wide beam circular polarization simultaneously with linear polarization in two close bands. This cross configuration brings good circular polarization to a loop antenna because it uses the transmission line mode of a folded dipole antenna. For these reasons, the antenna is named the Cross Spiral Antenna (CSA). In this paper, a basic structure and the principle of the CSA radiating circular polarization with one port feeding is explained. The prototype CSA, which is tuned to around 1.57GHz and 1.6GHz, is tested for verifying the effectiveness of the suggested antenna configuration.

High structural perfection, wafer uniformity, and reproducibility are key parameters for high-volume, low cost manufacture of resonant tunnelling diode (RTD) terahertz (THz) devices. Low-cost, rapid, and non-destructive techniques are required for the development of such devices. In this paper, we report photoluminescence (PL) spectroscopy as a non-destructive characterisation technique for high current densityInGaAs/AlAs/InP RTD structures grown by metal-organic vapour phase epitaxy (MOVPE) for THz applications. By using a PL line scanning technique across the edge of the sample, we identify characteristic luminescence from the quantum well (QW) and the undoped/n+ InGaAs layers. By using the Moss-Burstein effect, we are able to measure the free-electron concentration of the emitter/collector and contact layers in the RTD structure. Whilst the n+ InGaAs luminescence provides information on the doping concentration, information on the alloy composition and compositional variation is extracted from the InGaAs buffer layer. The QW luminescence provides information on the average well width and provides a monitor of the structural perfection with regard to interface and alloy disorder.