We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played only when the downloaded circuit is correctly combined (=interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. This paper describes the detailed architecture of the system and clarify the feasibility and effectiveness of the system. In addition, we discuss a fail-safe mechanism and future work necessary for the practical application of the system.

In air navigation, the rotation of aircraft results in the discontinuous tracking of GNSS signals. As the platform rotates, the GNSS signals are subject to blanking effects. To solve this problem, a ring-type antenna array is used to prevent signal discontinuity and a hypothesis-test based detection scheme is developed so that the correct antenna combination can be formed to provide uninterrupted reception of GNSS signals in the presence of blanking, noise, and interferences. A fixed threshold detection scheme is first developed by assuming that the statistics of the noise are known. It is shown that the scheme is capable of differentiating signal from noise at each antenna element. To account for the interference effect, a multiple hypothesis test scheme, together with an adaptive selection rule, is further developed. Through this detection and selection process, it is shown, through simulations, that the desired GNSS signals can be extracted and successfully tracked in the presence of blanking and co-channel interference.

At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

We describe a sub 100-mW H.264 MP@L4.1 integer-pel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 19201080 pixels at 30 fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90 nm CMOS design rule. Core size is 2.52.5 mm2. One core supports one-reference-frame and dissipates 48 mW at 1 V. Two core configuration consumes 96 mW for two-reference-frame search.

This paper proposes an efficient systolic array construction method for optimal planar systolic design of the matrix multiplication. By connection network adjustment among systolic array processing element (PE), the input/output data are jumping in the systolic array for multiplication operation requirements. Various 2-D systolic array topologies, such as square topology and hexagonal topology, have been studied to construct appropriate systolic array configuration and realize high performance matrix multiplication. Based on traditional Kung-Leiserson systolic architecture, the proposed "Jumping Systolic Array (JSA)" algorithm can increase the matrix multiplication speed with less processing elements and few data registers attachment. New systolic arrays, such as square jumping array, redundant dummy latency jumping hexagonal array, and compact parallel flow jumping hexagonal array, are also proposed to improve the concurrent system operation efficiency. Experimental results prove that the JSA algorithm can realize fully concurrent operation and dominate other systolic architectures in the specific systolic array system characteristics, such as band width, matrix complexity, or expansion capability.

Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.

This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-µm CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.

This paper presents a target location estimation method that can use a pair of leaky coaxial cables to determine the 2D coordinates of the target. Since convention location techniques using leaky coaxial cables can find a target location along the cable in 1D, they have been unable to locate it in 2D planes. The proposed method enables us to estimate target on a 2D plane using; 1) a beam-forming technique and 2) a reconstruction technique based on Hough transform. Leaky coaxial cables are equipped with numerous slots at regular interval, which can be utilized as antenna arrays that acts both as transmitters and receivers. By completely exploiting this specific characteristic of leaky coaxial cables, we carried out an antenna array analysis that performs in a beam-forming fashion. Simulation and experimental results support the effectiveness of the proposed target location method.

This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

For real time image processing, a readout circuit for an infrared focal plane array (IRFPA) involving a new edge detection technique has been proposed in this letter. A non-uniformity correction unit (NUC), essential in an IRFPA because of bad non-uniformity characteristics of IR sensors is eliminated in this circuit by using a noise tolerant edge detection technique. In addition, real time edge detection can be possible, because of pixel-level integration and parallel processing. The proposed readout circuit shows an approximately three to nine times better edge error rate than other available methods using pixel-level parallel processing.

The Earth will require sustainable electricity sources equivalent to 3 to 5 times the commercial power presently produced by 2050. Solar Power Satellite (SPS) is one option for meeting the huge future energy demand. SPS can send enormous amounts of power to the Earth as the form of microwave (MW). A highly efficient microwave power transmission (MPT) system is needed for SPS. A critical goal of SPS is to maintain highest Beam Efficiency (BE) because the microwaves from SPS will be converted to utility power unlike the MW from communication satellites. Another critical goal of SPS is to maintain Side Lobe Levels (SLL) as small as possible to reduce interference to other communication systems. One way to decrease SLL and increase BE is the edge tapering of a phased array antenna. However, tapering the excitation requires a technically complicated system. Another way of achieving minimum SLL is with randomly spaced element position but it does not guarantee higher BE and the determination of random element position is also a difficult task. Isosceles Trapezoidal Distribution (ITD) edge tapered antenna was studied for SPS as an optimization between full edge tapering and uniform amplitude distribution. The highest Beam Collection Efficiency (BCE) and lowest SLL (except maximum SLL) are possible to achieve in ITD edge tapering and ITD edge tapered antenna is technically better. The performance of ITD is further improved from the perspective of both Maximum Side Lobe Level (MSLL) and BE by using unequal spacing of the antenna elements. A remarkable reduction in MSLL is achieved with ITD edge tapering with Unequal element spacing (ITDU). BE was also highest in ITDU. Determination of unequal element position for ITDU is very easy. ITDU is a newer concept that is experimented for the first time. The merits of ITDU over ITD and Gaussian edge tapering are discussed.

A method for extracting a sound signal from a particular area that is surrounded by multiple ambient noise sources is proposed. This method performs several fixed beamformings on a pair of small microphone arrays separated from each other to estimate the signal and noise power spectra. Noise suppression is achieved by applying spectrum emphasis to the output of fixed beamforming in the frequency domain, which is derived from the estimated power spectra. In experiments performed in a room with reverberation, this method succeeded in suppressing the ambient noise, giving an SNR improvement of more than 10 dB, which is better than the performance of the conventional fixed and adaptive beamforming methods using a large-aperture microphone array. We also confirmed that this method keeps its performance even if the noise source location changes continuously or abruptly.

A compact arrayed-waveguide grating with small-bend waveguides incorporating air trenches and high mesa structures has been proposed. An 8-channel, 100-GHz-spacing silica arrayed-waveguide grating was fabricated, and its size was reduced dramatically to 1/4 of that of a conventional device.

In our application targeted here, four on-glass antenna elements are set in an automobile to improve the reception quality of mobile ISDB-T receiver. With regard to the directional characteristics of each antenna, we propose and implement a joint Pre-FFT adaptive array antenna and Post-FFT space diversity combining (AAA-SDC) scheme for mobile ISDB-T receiver. By applying a joint hardware and software approach, a flexible platform is realized in which several system configuration schemes can be supported; the receiver can be reconfigured on the fly. Simulation results show that the AAA-SDC scheme drastically improves the performance of mobile ISDB-T receiver, especially in the region of large Doppler shift. The experimental results from a field test also confirm that the proposed AAA-SDC scheme successfully achieves an outstanding reception rate up to 100% while moving at the speed of 80 km/h.

The concept of placing enormous Solar Power Satellite (SPS) systems in space represents one of a handful of new technological options that might provide large scale, environmentally clean base load power to terrestrial markets. Recent advances in space exploration have shown a great need for antennas with high resolution, high gain and low side lobe level (SLL). The last characteristic is of paramount importance especially for the Microwave Power Transmission (MPT) in order to achieve higher transmitting efficiency (TE) and higher beam collection efficiency (BCE). In order to achieve low side lobe levels, statistical methods play an important role. Various interesting properties of a large antenna arrays with randomly, uniformly and combined spacing of elements have been studied, especially the relationship between the required number of elements and their appropriate spacing from one viewpoint and the desired SLL, the aperture dimension, the beamwidth and TE from the other. We propose a new unified approach in searching for reducing SLL by exploiting the interaction of deterministic and stochastic workspaces of proposed algorithms. Our models indicate the side lobe levels in a large area around the main beam and strongly reduce SLL in the entire visible range. A new concept of designing a large antenna array system is proposed. Our theoretic study and simulation results clarify how to deal with the problems of side lobes in designing a large antenna array, which seems to be an important step toward the realization of future SPS/MPT systems.

In this letter, we analyze symbol error probability (SEP) and diversity gain of orthogonal space-time block codes (OSTBCs) in spatially correlated Rician fading channel. We derive the moment generating function (MGF) of an effective signal-to-noise ratio (SNR) at the receiver and use it to derive the SEP for M-PSK modulation. We use this result to show that the diversity gain is achieved by the product of the rank of the transmit and receive correlation matrix, and the loss in array gain is quantified as a function of the spatial correlation and the line of sight (LOS) component.

A metallic waveguide with dual in-line dielectric rods can propagate electromagnetic waves more than two times higher than the cutoff frequency region and without higher modes [1]. If the straight portion in the waveguide has even symmetry, then dielectric rods are only required in the bent portion. Connection losses between the portions are improved by adding other dielectric rods.

We investigate the effects of timing misalignment and imperfect array weight vector generation on the antenna array (AA)-aided uplink synchronous DS-CDMA system. Previous works have assumed perfect uplink synchronization among first path's receiving timing and perfect array weight vector calculation. Unfortunately, practical system will experience of timing control error (TCE) and array weight error (AWE). Accordingly, this letter undertakes an analysis of the impacts of TCE and AWE, evaluating a closed form BER performance considering the important factors such as the number of antennas, the variance of AWE and the misalignment factor as a measure of the TCE in dispersive Rayleigh multipath fading channel. Additionally, the scenario of synchronous uplink with the cell-site AA is compared with asynchronous scheme. Numerical results show that the performance in the synchronous uplink can be further improved, even at high levels of AWE and TCE.

We previously proposed a method of sound source and microphone localization. The method estimates the locations of sound sources and microphones from only time differences of arrival between signals picked up by microphones even if all their locations are unknown. However, there is a problem that some estimation results converge to local minimum solutions because this method estimates locations iteratively and the error function has multiple minima. In this paper, we present a new iterative method to solve the local minimum problem. This method achieves accurate estimation by selecting effective initial locations from many random initial locations. The computer simulation and experimental results demonstrate that the presented method eliminates most local minimum solutions. Furthermore, the computational complexity of the presented method is similar to that of the previous method.

This letter describes a millimeter wave slot array antenna using a rectangular waveguide and a ferrite. The radiation direction of the leaky wave from the slot array can be scanned by applying a dc bias magnetic field parallel to the ferrite. The radiation pattern of a prototype antenna has been measured at 40 GHz. The main beam direction changes from 10 to 3 degree by the bias magnetic field of 0.73 T.