The mechanism of UV-excited dry cleaning using photoexcited chlorine radicals has been investigated for removing iron and aluminum contamination on a silicon surface. The iron and aluminum contaminants with a surface concentration of 1013 atoms/cm2 were intentionally introduced via an ammonium-hydrogenperoxide solution. The silicon etching rates from the Uv-excited dry cleaning differ depending on the contaminants. Fe and Al can be removed in the same manner. The removal of Fe and Al is highly temperature dependent, and is little affected by the silicon etching depth. Both Fe and Al on the silicon surface were completely removed by UV-excited dry cleaning at a cleaning temperature of 170, and were decreased by two orders of magnitude from the initial level when the surface was etched only 2 nm deep.

As part of Hitachi's development of clean semiconductor processing equipment, the Fluids Modeling Group of the Mechanical Engineering Research Laboratory is developing a computer model, CONTAMINATE, for simulating contamination of wafers in chemical vapor deposition (CVD) systems. CONTAMINATE is based on a 2D implementation of the SIMPLER algorithm for simulating convection/diffusion transport processes. The new model includes modules for simulating fluid flow, heat transfer, chemical reactions, and gas-phase formation and deposition of clusters and particles. CONTAMINATE outputs property fields and estimates of various film quality indices. Using CONTAMINATE we simulated a SiH4: O2: N2 gas mixture at 300 K flowing over a wafer heated to 700 K. System pressures were varied from 1-100 torr and SiH4 pressures from 0.1 to 10 torr. Deposition characteristics are in qualitative agreement with actual systems and are summarized as follows: (1) No particles larger than 0.1µm deposited for any of the conditions tested. (2) Film damage occurred above 10 torr, but no damage occurred below 10 torr. (3) Increasing SiH4 pressure at constant system pressure eliminated particle deposition because particles grew large enought that thermophoresis blocked particle diffusion. (4) Conformal deposition of featured surfaces was achieved only at 1 torr. (5) Film thickness variation over the diameter of the wafer was 15% at 100 torr, 3% at 10 torr, and 1% at 1 torr.

The motion of particles in low-pressure chemical vapor deposition (LPCVD) (0.4 Torr) equipment has been investigated by a numerical simulation. The effects of wafer orientation, electrostatic forces, and thermophoresis were evaluated. Horizontal surface-down processing and vertical processing can reduce particulate contamination remarkably compared with horizontal surface-up processing. Static electricity control is essential. Weakly charged wafers (several V to several 10 V) can significantly increase submicron particle deposition. In the absence of electrical forces, thermophoresis prevents deposition of particles in the size range 0.03 µmDp0.6 µm, when the temperature difference between the wafer surface and the gas inlet temperature exceeds 100. Deposition of particles smaller than 0.03 µm still occurs by diffusion.

Chemical structures of native oxides formed during wet chemical treatments of silicon surfaces were investigated using X-ray Photoelectron Spectroscopy (XPS) and Fourier Transformed Infrared. Attenuated Total Reflection (FT-IR-ATR). It was found that the amounts of Si-H bonds in native oxide and at native oxide/ silicon interface are negligibly small in the case of native oxides formed in H2SO4-H2O2 solution. Based on this discovery, it was found that native oxides can be characterized by the amount of Si-H bonds in the native oxide and the combination of various wet chemical treatments with the treatment in NH4OH-H2O2-H2O solution results in the drastic decrease in the amount of Si-H bonds in the native oxides.

Thermal desorption spectroscopy (TDS) is applied to analyze the oxidation reactions of hydrogen-terminated Si(100) surfaces in both the heating and cooling processes after hydrogen desorption. The oxidation reaction of oxygen and water with a silicon surface after hydrogen desorption shows hysteresis in the heating and cooling processes. In the cooling process, oxidation finishes when the silicon surface is adequately oxidized to about a 10 thickness. Oxidation continues to occur at lower temperatures when the total volume of oxygen and water is too small to saturate the bare silicon surface. The reaction of water with silicon releases hydrogen at more than 500. Hydrogen does not adsorb on the silicon oxide surface. A trace amount of oxygen, less than 110-6 Torr, roughens the surface.

The increase of surface microroughness on Si substrate degrades the electrical characteristics such as the dielectric breakdown field intensity (EBD) and charge to break-down (QBD) of thin oxide film. It has been found that the surface microroughness increases in the wet chemical process, particularly in NH4OH-H2O2-H2O cleaning (APM cleaning). It has been revealed that the surface microroughness does not increase at all if the NH4OH mixing ratio in NH4OH-H2O2-H2O solution is reduced from the conventional level of 1:1:5 to 0.05:1:5, and the room temperature ultrapure water rinsing is introduced right after the APM cleaning. At the same time, the APM cleaning with NH4OH-H2O2-H2O mixing ratio of 0.05:1:5 has been very effective to remove particles and metallic impurities from the Si surface. The surface microroughness dominating the electrical properties of very thin oxide films is strictly influenced by the wafer quality. The increase of surface microroughness due to the APM cleaning has varied among the wafer types such as Cz, FZ and epitaxial (EPI) wafers. The increase of surface microroughness in EPI wafer was very much limited, while the surface microroughness of FZ and Cz wafers gradually increase. As a result of investigating the amount of diffused phosphorus atoms into these wafers, the increase of the surface microroughness in APM cleaning has been confirmed to strongly depend on the silicon vacancy cluster concentration in wafer. The EPI wafer having low silicon vacancy concentration is essentially revealed superior for future sub-half-micron ULSI devices.

An extremely accurate and very wide-band quadrature modulator IC fabricated on a single chip using bipolar technology is presented. The characteristics of this quadrature modulator IC are much superior to conventional ones (modulation phase error and deviation from quadrature is about 1/10), and this IC is applicable to high modulation schemes such as 256 QAM. In this circuit, the phase difference between local signals input to each of two balanced modulators is detected by a phase detector, and a variable phase shifter in the local port is controlled automatically by the detected signals. This, along with the use of a wide-band variable phase shifter, enables the phase difference between the local signals input to the balanced modulators to be adaptively controlled to 90 degrees in wide frequency bands. In addition, a design method for the balanced modulators to obtain small modulation phase error is described. Based on this design method, a highly accurate quadrature modulator IC was fabricated, in which two balanced modulators, the phase detector, and the variable phase shifter were integrated on a single chip. Phase deviation from quadrature in the local signals was reduced to less than 0.3 degrees in the wide frequency bands of more tham 60 MHz. The modulation phase error of the balanced modulators wes less than 0.2 degrees at 140 MHz, and less than 2.5 degrees at up to 1.3 GHz.

A method for sweeping frequency ranges of over 130GHz within a tuning range of 30nm, without mode hopping, has been realized. The optical frequency is swept with a fine translation-rotation grating drive which uses a new, simplified operation method and a thermally controlled semiconductor laser system.

The effect of the externally reflected light on the mode partition characteristics of 1.3 µm Fabry-Perot laser diodes is studied experimentally and numerically. It is observed that the k-value increases monotonically with the DC bias current and the external reflection coefficient. Based on these experimental results, a numerical model to study the mode partition characteristics of laser diodes in the presence of external reflections is developed. The results calculated using this model agree well with the experimental ones. It is found that the mode partition noise is mainly caused by the interference between the light in the laser diode and the reflected light, and also by the fluctuations of the induced emission and absorption. In the time domain, their contribution to the mode partition noise is almost localized in the time region within 0.1nsec at the time when the optical pulse turns on.

An automatic optimization system for semiconductor devices has been built-up by fully interfacing an optimizer and a device-analysis code supplemented with sensitivity analysis. The device-analysis code is thought of as a part of a pipeline of simulators. The latters are regarded as subprocesses by the optimizer, which controls their I/O stream. The action of the pipeline is iterated until the optimum set of design parameters is determined. An important feature of the system is that all the derivatives required in the sensitivity analysis are calculated analytically, this providing a substantial improvement in both the numerical accuracy and computational efficiency, and making the scheme attractive from the application standpoint. A few examples of optimization of MOS devices are shown and the performance is reported, indicating that a system of this kind can usefully be exploited in a design environment.

This paper is concerned with the stress simulation of a LOCOS structure during not only oxidation but also the subsequent cooling down based on viscoelastic stress modeling. A viscoelastic model is successfully applied to the oxide, nitride and silicon substrate for a LOCOS structure. Thermal stress is also taken into account during the cooling down process. The viscoelastic deformation problem of all the three materials for the LOCOS structure are solved by a two-dimensional finite element method. It is the first time to show that the stress values after cooling down to room temperature are much higher than those right after oxidation. It is also shown that varying the cooling down rates results in the different stress values after cooling down.

We have developed a new model to analyze the thermal failure mechanism due to electrical-over-stress (EOS) for two-dimensional planar pn-junction structures where the failure power is proportional to about 1/5 power of the failure time. We adopted a pseudo two-dimensional numerical simulation method where a pn-junction diode is divided into small elements and represented by a circuit network composed of many minute resistors and diodes. The failure mechanism studied by Wunsch and Bell, that is one of many studies for one-dimensional pn-diodes, is not valid for the case of two-dimensional pn-junction, such as a planar type junction. On the contrary, the failure mechanism was found to be much correlative with the junction structure, especially the impurity concentration in the substrate in the two-dimensional case. When the impurity concentration in the substrate is high enough (e.g. Nsub1017[cm-3]), the breakdown occurs at the whole junction. The heat transfer is one-dimensional and the failure power is proportional to about 1/2 power of the failure time, which is well known results reported by many researchers: e.g. Wunsch &Bell. On the other hand, when the impurity concentration in the substrate is low enough (e.g. Nsub1016[cm-3]), the breakdown occurs locally at the junction edge. The heat transfer is two-dimensional and the failure power is in proportion to about 1/5 power of the failure time.