Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

Recently, high-dose implantation and low temperature annealing have become one of the key techniques in shallow junction formation. To fabricate shallow junction in quarter-micron CMOS VLSIs, it is well known being important to evaluate the transient enhanced diffusion (TED) of implanted dopants at low temperature furnace annealing, which is caused by the damages of implantation. We have newly studied the TED phenomena by a compact empirical method. This approach has merits of simplicity and better physical intuition, because we can use only minimal parameters to describe the TED phenomena. The other purpose of this work is to evaluate two-dimensional transient enhanced diffusion focusing on phosphorus implant and furnace annealing. Firstly, we defined effective diffusivity of the TED and determined extraction procedure of the model parameters. Number of the TED model parameters is minimized to two, which describe effective enhanced diffusivity and its activation energy. The parameters have been extracted from SIMS profile data obtained from samples which range 1013-31015 cm-2 and 850-950 for phosphorus implanted dose and annealing temperature, respectively. Simulation results with the extracted transient enhanced diffusion parameters show good agreements well with the SIMS data within 2% RMS-error. Critical doses for phosphorus enhanced diffusion have been determined in 950 annealing condition. No transient enhanced diffusion is observed at 950 under the implant dose of 11013 cm-2. Also the transient enhanced diffusivity is leveled off over the dose of 11014 cm-2. It is seen that the critical dose in TED phenomena might be temperature dependent to a certain extent. We have also verified that two-dimensional effect of the TED phenomena experimentally. Two-dimensional phosphorus n- layer is chosen to verify the simulation. It was concluded that the TED has isotropic nature in phosphorus n- diffusion formation.

Narrow emitter effects in self-aligned bipolar transistors are discussed. Besides the increase of a non-ideal base current, the decrease of an ideal base current is newly observed, and a consequent fluctuation of the current gain becomes wider in the smaller emitter geometry. Both phenomena are attributed to the reduction of an emitter-impurity concentration.

A new effect of barrier metal laid under 1st aluminum layer on electromigration has been found in interconnect vias. This effect can be explained by Si nodules at vias. Stress induced open failure occurred at viaholes and depends on the size of the vias. Stress-migration at vias can be prevented by TiN barrier metal between 1st and 2nd metals. Reliability of electro- and stress-migration at interconnect vias can be explosively improved by using TiN barrier metal.

A 10 GHz MMIC predistortion linearizer fabricated on a single chip is demonstrated for the first time. It employs less hybrid circuits compard with conventional devices, and is suitable for miniaturization. The total chip size of the fabricated MMIC is about 3.5 mm3.0 mm. The distortion reduction effect is examined using this linearizer. The improvement in IM3 is more than 15 dB between 10.45 GHz and 10.70 GHz, and more than 8 dB between 10.05 GHz and 10.90 GHz.

In order to develop silicon ICs operating up to above 450, Integrated Injection Logic (IIL) was chosen. A new structure for IIL was designed through experimental and theoretical studies of pn junctions, transistors, and IIL at high temperatures. A 5-µm design rule was used. The new IIL was fabricated by a specially developed combined process of ion implantation and low temperature epitaxy. The IIL was fully operational from room temperature to 454, and the output amplitude of a nine-stage ring oscillator was about 30 mV at 454. The minimum delay time of the IIL was 22 nsec at 454. The minimum power-delay product was 11 pJ and was one-third of that for IILs fabricated by 10-µm rule at 50.

For the effective control of microwaves in the frequency domain, we propose a new method utilizing current distributions of standing waves on the terminated microstrip line. We analized a short ended microstrip line using the (FD)2TD method to indicate the effectiveness of our proposal. Further we proposed an optically controlled microstrip filter as an application of this method.

This letter proposes a microstrip band elimination filter having an optically controlled small gap on a resonant section for the shift of the eliminated frequency range using the semiconductor plasma. The basic characteristics of this filter are analized theoretically utilizing the (FD)2TD method.

This paper reports on broad-range wavelength tuning characteristics of DBR lasers which make use of a newly proposed multiple-phase-shift super structure grating (SSG). The reflection characteristics of the SSG reflector are analyzed theoretically. We found that the SSG reflector has periodic sharp reflection peaks each with high reflectivities thus making it a suitable wavelength selective reflector for single-mode lasers. The expected characteristics were evident in multiple-phase-shift SSGs fabricated using a new method which involves multiple-phase-shift insertion. DBR lasers with multiple-phase-shift SSGs were fabricated and their wavelength tuning characteristics were studied. The maximum tuning range is 105 nm in the single longitudinal mode under a CW condition. Dynamic single mode operation was also observed throughout the tuning range.

We have achieved the room temperature cw lasing operation of GaInAsP/InP surface emitting lasers for the first time. By employing a buried heterostructure with 1.3 µm range active region and a MgO/Si heat sink mirror, cw operation was obtained up to 14 with the threshold current of 22 mA.

The small-signal negative resistance of QWITT (Quantum Well Transit-Time) diodes is calculated including the effect of field-dependent diffusion coefficient in the frequency range of 10 to 300 GHz. The drift velocity transient effect is also included. The result is compared with those obtained by using constant diffusion coefficients at average electric fields.

In this letter, the effectiveness of the quasi-TEM approximation is studied for the microstrip line including optically induced semiconductor plasma region. This approximation is considered to be efficient under several restrictions such as the upper limit of the microwave frequency and the plasma density.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

The generation mechanism for excess intensity noise due to optical feedback is analyzed theoretically and experimentally. Modal rate equations under the weakly coupled condition with external feedback are derived to include the mode competition phenomena in DFB and Fabry-Perot lasers. We found that the sensitivity of the external feedback strongly depends on design parameters of structure, such as the coupling constant of the corrugation, the facet reflection and the phase relation between the corrugation and the facet. A DFB laser whose oscillating wavelength is well adjusted to Bragg wavelength through insertion of a phase adjustment region becomes less sensitive to external optical feedback than a Fabry-Perot laser, but other types of DFB lasers revealing a stop band are more sensitive than the Fabry-Perot laser.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.