Long-wavelength 1.3 µm GaInAsP/InP vertical cavity surface-emitting lasers (VCSELs) have been demonstrated in an array configuration. With the strong current confinement by a buried heterostructure and the efficient optical feedback by a dielectric cavity, five VCSEL elements in a 24 array operated at room temperature with 5 mW total power output and wavelength error within 5%. The stacked planar optics including the VCSEL array is a promising optical transmitter in ultra large scale parallel optical communication systems.

In this paper, an electrostatic actuator with electret is proposed. Electrets are the electrical equivalent of magnets. They are dielectric's carrying a non equilibrium permanent space charge or polarization distribution. This distribution can create either an external electric field or internal properties such as piezo or pyroelectricity. In the first case it is possible to make new types of electrostatic actuators by the external electric field. An electrostatic relay with electret is fabricated to demonstrate the possibility of an electrostatic actuator with electret. The size of relay is 5.2 mm11.5 mm. Its amature beam is 50 µm thick, 2.9 mm wide, 6.3 mm long, and acts as a moving electrode. Facing it, the stationary electrode is 20 µm away from the moving electrode. On the stationary electrode, new type of electret made from SiO2 is deposited. We have succeeded in making the armature operate at low applied voltage 20 V. On the same structure without electret, we need more than 120 V to make the same armature operation. We have also succeeded in making the armature latching.

Laser diodes for optical interconnections are ideally high speed, work over a wide temperature range, and are simple to bias. This paper reports high bit-rate modulation with nearly zero bias with very low threshold 1.3µm-wavelength laser diodes over a wide temperature range. At the high temperature of 80, lasing delay was 165 ps with nearly zero bias. We demonstrated 2.5 Gbit/s modulation over a wide temperature range. Eye opening was over 34% of one time slot.

Fabrication methods of novel silicon quantum wires and dots using anisotropic wet chemical etching and thermal oxidation are newly proposed. The method realizes fine Si quantum wires, which are fully surrounded by the thermal SiO2 without any defects. The wires are straight and the Si/SiO2 interfaces are fairly flat. The 10 nm width wires are confirmed by Transmitting Scanning Microscopy observation in minimum size. The fine quantum dots are also fabricated using this method. The characteristics of the wires are investigated and the current oscillations in variation with the gate voltage are observed in low temperature. We believe the origin of these oscillations arise from one-dimensional subband conduction.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.

We propose, for the first time, highly reliable flash-type EEPROM cell fabrication using in-situ multiple rapid thermal processing (RTP) technology. In this study, rapid thermal oxynitridation tunnel oxide (RTONO) film formations followed by in-situ arsenic (As)-doped floating-gate polysilicon growth by rapid thermal chemical vapor deposition (RTCVD) technologies are fully utilized. The results show that after 5104 program/erase (P/E) endurance cycles, the conventional cell shows 65% narrowing of the threshold voltage (Vt) window, whereas the RTONO cell indicates narrowing of less than 20%. A large number of nitrogen atoms (1020 atoms/cm3) are confirmed by secondary ion mass spectrometry (SIMS), pile up at the SiO2/Si interface and distribute into bulk SiO2. It is considered that in the RTONO film stable Si-N bonds are formed which minimize electron trap generation as well as the neutral defect density, resulting in lower Vt shifts in P/E stress. In addition, the RTONO film reduces the number of hydrogen atoms because of final N2O oxynitridation. The SIMS data shows that by the in-situ RTCVD process As atoms (91020 atoms/cm3) are incorporated uniformly into 1000--thick film. Moreover, the RTCVD polysilicon film indicates an extremely flat surface. The time-dependent dielectric breakdown (TDDB) characteristics of interpoly oxide-nitride-oxide (ONO) film exhibited no defect-related breakdown and 5 times longer breakdown time as compared to phosphorus-doped polysilicon film. Therefore, the flash-EEPROM cell fabricated has good charge storing capability.

In this paper, authors discuss on a lexicon directed algorithm for recognition of unconstrained handwritten words (cursive, discrete, or mixed) such as those encountered in mail pieces. The procedure consists of binarization, presegmentation, intermediate feature extraction, segmentation recognition, and post-processing. The segmentation recognition and the post-processing are repeated for all lexicon words while the binarization to the intermediate feature extraction are applied once for an input word. This algorithm is essentially non hierarchical in character segmentation and recognition which are performed in a single segmentation recognition process. The result of performance evaluation using large handwritten address block database, and algorithm improvements are described and discussed to achieve higher recognition accuracy and speed. Experimental studies with about 3000 word images indicate that overall accuracy in the range of 91% to 98% depending on the size of the lexicon (assumed to contain correct word) are achievable with the processing speed of 20 to 30 word per minute on typical work station.

Control of electronic states of dye molecules (organic semiconductors) by introducing appropriate substituent groups has been examined. NH2 (electron-releasing group) and NO2 (electron-withdrawing group) were introduced in thiacarbocyanine dye to modify the electronic states of the dyes. The effect of modification was examined based on the properties of photoelectric cells made by the dye derivatives. Clear increase in photocurrent, more than ten times, was observed when modified dyes were used instead of the original dye. The result shows that the introduction of substituent groups for organic semiconductors is quite effective to control the electronic states, and the introduction can be regarded as doping in molecular level.

A convenient method for determining emitter and base resistances from small signal measurements has been developed. This method is based on Neugroschel's method, but the frequency has been varied instead of varying β0. It is demonstrated that the base resistance was successfully extracted. The extracted emitter resistance depended on the collector current because of the difference between the exact gm value and the approximated one, IC/VT. It has also been shown that the proposed method is more robust than the conventional impedance-circle method even when cross-talk occurs.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

When intermetal oxide film which contains much water deposited on MOSFET, degradation of hot carrier characteristics is enhanced. This mechanism is considered to be as follows. During the annealing process water is desorbed from the intermetal oxide. The desorbed water reaches the MOSFET and eventually hydrogens terminate silicon dangling bonds in the gate oxide. This paper describes a new approach which uses ESR to analyze this mechanism. The ESR measurement of number of the silicon dangling bonds in undoped polysilicon lying under the intermetal oxide shows that water diffuses from intermetal oxide to MOSFET during the annealing process. The water diffusion is blocked by introduction between the polysilicon and the intermetal oxides of P-SiN layer or CVD SiO2 damaged by implantation.

Operation characteristics of tapered-waveguide traveling wave semiconductor laser amplifier (TTW-SLA) are calculated in terms of quasi adiabatic single mode propagation, signal gain and saturation output power, device efficiency(the efficiency of conversion between the electrical and amplified optical power), and amplified spontaneous emission (ASE) power, and their dependences on the shape of the taper are compared for linear, quadratic, Gaussian and exponential functions, It was found that in the allowed quasi adiabatic single mode propagation condition, linear and Gaussian TTW-SLA have higher saturation output power property, while the exponential TTW-SLA has higher device efficiency property and lower ASE noise of about 0.1 times that of a broad type TW-SLA.

New detection method of passivation defect was studied. The method was the Cu decoration method without bias (bias-free Cu decoration). As the result of comparison with conventional method, it was found that a bias-free Cu decoration method was effective, sensitive and simple. In this method, the difference of humidity resistance induced by poor passivation coverage could be evaluated.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.