Low-temperature bonding methods of optoelectronic chips, such as laser diodes (LD) and photodiode (PD) chips, have been the focus of much interest to develop highly functional and compact optoelectronic devices, such as microsensors and communication modules. In this paper, room-temperature bonding of the optoelectronic chips with Au thin film to coined Au stud bumps with smooth surfaces (Ra: 1.3nm) using argon and hydrogen gas mixture atmospheric-pressure plasma was demonstrated in ambient air. The die-shear strength was high enough to exceed the strength requirement of MIL-STD-883F, method 2019 (×2). The measured results of the light-current-voltage characteristics of the LD chips and the dark current-voltage characteristics of the PD chips indicated no degradation after bonding.

Protecting control planes in networking hardware from high rate packets is a critical issue for networks under operation. One common approach for conventional networking hardware is to offload expensive functions onto hard-wired offload engines as ASICs. This approach is inadequate for OpenFlow networks because it restricts a certain amount of flexibility for network control that OpenFlow tries to provide. Therefore, we need a control plane protection mechanism in OpenFlow switches as a last resort, while preserving flexibility for network control. In this paper, we propose a mechanism to filter out Packet-In messages, which include packets handled by the control plane in OpenFlow networks, without dropping important ones for network control. Switches record values of packet header fields before sending Packet-In messages, and filter out packets that have the same values as the recorded ones. The controllers set the header fields in advance whose values must be recorded, and the header fields are selected based on controller design. We have implemented and evaluated the proposed mechanism on a prototype software switch, concluding that it dramatically reduces CPU loads on switches while passes important Packet-In messages for network control.

The alternating direction implicit (ADI) method is proposed for low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. The low-rank solution is expressed by Cholesky factor that is similar to that of Cholesky factorization for linear system of equations. The Cholesky factor is represented in a real form so that it is useful for balanced truncation of sparsely connected RLC networks. Moreover, we show how to determine the shift parameters which are required for the ADI iterations, where Krylov subspace method is used for finding the shift parameters that reduce the residual error quickly. In the illustrative examples, we confirm that the real Cholesky factor certainly provides low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. Effectiveness of the shift parameters determined by Krylov subspace method is also demonstrated.

Many selected mapping (SLM) schemes have been proposed to reduce the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) signal sequences. In this paper, an efficient selection (ES) method of the OFDM signal sequence with minimum PAPR among many alternative OFDM signal sequences is proposed; it supports various SLM schemes. Utilizing the fact that OFDM signal components can be sequentially generated in many SLM schemes, the generation and PAPR observation of the OFDM signal sequence are processed concurrently. While the u-th alternative OFDM signal components are being generated, by applying the proposed ES method, the generation of that alternative OFDM signal components can be interrupted (or stopped) according to the selection criteria of the best OFDM signal sequence in the considered SLM scheme. Such interruption substantially reduces the average computational complexity of SLM schemes without degradation of PAPR reduction performance, which is confirmed by analytical and numerical results. Note that the proposed method is not an isolated SLM scheme but a subsidiary method which can be easily adopted in many SLM schemes in order to further reduce the computational complexity of considered SLM schemes.

Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

In distributed storage systems, codes with lower repair locality are much more desirable due to their superiority in reducing the disk I/O complexity of each repair process. Motivated partially by both codes with information (r,δ1)c locality and codes with cooperative (r,l) locality, we propose the concept of codes with information (r,l,δ) locality in this paper. For a linear code C with information (r,l,δ) locality, values at arbitrary l information coordinates of an information set I can be recovered by connecting any of δ existing pairwise disjoint local repair sets with size no more than r, where a local repair set of l coordinates is defined as the set of some other coordinates by which one can recover the values at these l coordinates. We derive a lower bound on the codeword length n for [n,k,d] linear codes with information (r,l,δ) locality. Furthermore, we indicate its tightness for some special cases. Particularly, some existing results can be deduced from our bound by restriction on parameters.

Web Service Business Process Execution Language (BPEL) has become the de facto standard for developing instant service-oriented workflow applications in open environment. The correctness and reliability of BPEL processes have gained increasing concerns. However, the unique features (e.g., dead path elimination (DPE) semantics, parallelism, etc.) of BPEL language have raised enormous problems to it, especially in path feasibility analysis of BPEL processes. Path feasibility analysis of BPEL processes is the basis of BPEL testing, for it relates to the test case generation. Since BPEL processes support both parallelism and DPE semantics, existing techniques can't be directly applied to its path feasibility analysis. To address this problem, we present a novel technique to analyze the path feasibility for BPEL processes. First, to tackle unique features mentioned above, we transform a BPEL process into an intermediary model — BPEL control flow graph, which is proposed to abstract the execution flow of BPEL processes. Second, based on this abstraction, we symbolically encode every path of BPEL processes as some Satisfiability formulas. Finally, we solve these formulas with the help of Satisfiability Modulo Theory (SMT) solvers and the feasible paths of BPEL processes are obtained. We illustrate the applicability and feasibility of our technique through a case study.

Many actual systems, e.g. computer programs, can be modeled as a subclass of Petri nets, called bridge-less workflow nets. For bridge-less workflow nets, we revealed the following properties: (i) any acyclic bridge-less workflow net is free choice; (ii) an acyclic bridge-less workflow net is sound iff it is well-structured; and (iii) any sound bridge-less workflow net is well-structured. We also proposed a necessary and sufficient condition to decide whether a given workflow net is bridge-less, and then constructed a polynomial-time procedure for it.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

Workflow nets (WF-nets for short) are a mathematical model of real world workflows. A WF-net is often updated in accordance with the change of real world. This may cause places that are redundant from the viewpoint of the behavior. Such places are called implicit. We first proposed a necessary and sufficient condition to find implicit places. Then we proved that removing of implicit places is a reduction operation which forms branching bisimilarity. We also constructed an algorithm for the reduction. Next, we applied the proposed reduction operation to WF-net refactoring. Then we showed the usefulness of the proposed refactoring with two examples.

Detecting small infrared targets is a difficult but important task in highly cluttered coastal surveillance. The paper proposed a method called low-rank and sparse decomposition based frame difference to improve the detection performance of a surveillance system. First, the frame difference is used in adjacent frames to detect the candidate object regions which we are most interested in. Then we further exclude clutters by low-rank and sparse matrix recovery. Finally, the targets are extracted from the recovered target component by a local self-adaptive threshold. The experiment results show that, the method could effectively enhance the system's signal-to-clutter ratio gain and background suppression factor, and precisely extract target in highly cluttered coastal scene.

Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.

In modern communication systems, it is a critical and challenging issue for existing carrier tracking techniques to achieve near-ideal carrier synchronization without the help of pilot signals in the case of symbol rate sampling and low signal-to-noise ratio (SNR). To overcome this issue, this paper proposes an effective carrier frequency and phase offset tracking scheme which has a robust confluent synchronization architecture whose main components are a digital frequency-locked loop (FLL), a digital phase-locked loop (PLL), a modified symbol hard decision block and some sampling rate conversion blocks. As received signals are sampled at symbol baud rate, this carrier tracking scheme is still able to obtain precise estimated values of carrier synchronization parameters under the condition of very low SNRs. The performance of the proposed carrier synchronization scheme is also evaluated by using Monte-Carlo method. Simulation results confirm the feasibility of this carrier tracking scheme and demonstrate that it ensures that both the rate-3/4 irregular low-density parity-code (LDPC) coded system and the military voice transmission system utilizing the direct sequence spread spectrum (DSSS) technique achieve satisfactory bit-error rate (BER) performance at correspondingly low SNRs.

Analog and digital collaborative design techniques for wireless SoCs are reviewed in this paper. In wireless SoCs, delicate analog performance such as sensitivity of the receiver is easily degraded due to interferences from digital circuit blocks. On the other hand, an analog performance such as distortion is strongly compensated by digital assist techniques with low power consumption. In this paper, a sensitivity recovery technique using the analog and digital collaborative design, and digital assist techniques to achieve low-power and high-performance analog circuits are presented. Such analog and digital collaborative design is indispensable for wireless SoCs.

Traditional low-rank feature lose the temporal information among action sequence. To obtain the temporal information, we split an action video into multiple action subsequences and concatenate all the low-rank features of subsequences according to their time order. Then we recognize actions by learning a novel dictionary model from concatenated low-rank features. However, traditional dictionary learning models usually neglect the similarity among the coding coefficients and have bad performance in dealing with non-linearly separable data. To overcome these shortcomings, we present a novel similarity constrained discriminative kernel dictionary learning for action recognition. The effectiveness of the proposed method is verified on three benchmarks, and the experimental results show the promising results of our method for action recognition.

In this paper, an iterative optimal method is proposed to design the prototype filters for a fast filter bank (FFB) with low complexity, aiming to control the optimum ripple magnitude tolerance of each filter according to the overall specifications. This problem is formulated as an optimization problem for which the total number of multiplications is to be minimized subject to the constrained ripple in the passband and stopband. In the following, an iterative solution is proposed to solve this optimization problem for the purpose of obtaining the impulse response coefficients with low complexity at each stage. Simulations are conducted to verify the performance of the proposed scheme and show that compared with the original method, the proposed scheme can reduce about 24.24% of multiplications. In addition, the proposed scheme and the original method provide similar mean square error (MSE) and the mean absolute error (MAE) of the frequency response.

Explicit evaluation of the rate-distortion function has rarely been achieved when it is strictly greater than its Shannon lower bound since it requires to identify the support of the optimal reconstruction distribution. In this paper, we consider the rate-distortion function for the distortion measure defined by an ε-insensitive loss function. We first present the Shannon lower bound applicable to any source distribution with finite differential entropy. Then, focusing on the Laplacian and Gaussian sources, we prove that the rate-distortion functions of these sources are strictly greater than their Shannon lower bounds and obtain upper bounds for the rate-distortion functions. Small distortion limit and numerical evaluation of the bounds suggest that the Shannon lower bound provides a good approximation to the rate-distortion function for the ε-insensitive distortion measure. By using the derived bounds, we examine the performance of a scalar quantizer. Furthermore, we discuss variants and extensions of the ε-insensitive distortion measure and obtain lower and upper bounds for the rate-distortion function.

In this paper, we present a modified image rejection method that uses imbalance compensation techniques for phase and gain in low-intermediate frequency (IF) software-defined radio (SDR) receivers. In low-IF receivers, the image frequency signal interferes with the desired signal owing to the phase and gain imbalances caused by analog devices. Thus, it is difficult to achieve the required image rejection ratio (IRR) of over 60dB without compensation. To solve this problem, we present modified blind compensation techniques based on digital signal processing using a feedback control loop with a practical computation process. The modified method can reduce the complexity when a hardware logic circuit is used, like an FPGA. The simulation and experimental results verify that the modified method achieves an IRR greater than 50-60dB for both the carrier and the modulated waves.

The ordered successive interference cancellation (OSIC) detector based on the minimum mean square error (MMSE) criterion has been proved to be a low-complexity detector with efficient bit error rate (BER) performance. As the well-known MMSE-Based OSIC detector, the MMSE-Based vertical Bell Laboratories Layered Space-Time (VBLAST) detector, whose computational complexity is cubic, can not attain the minimum BER performance. Some approaches to reducing the BER of the MMSE-Based VBLAST detector have been contributed, however these improvements have large computational complexity. In this paper, a low complexity MMSE-Based OSIC detector called MMSE-OBEP (ordering based on error probability) is proposed to improve the BER performance of the previous MMSE-Based OSIC detectors, and it has cubic complexity. The proposed detector derives the near-exact error probability of the symbols in the MMSE-Based OSIC detector, thus giving priority to detect the symbol with the smallest error probability can minimize the error propagation in the MMSE-Based OSIC detector and enhance the BER performance. We show that, although the computational complexity of the proposed detector is cubic, it can provide better BER performance than the previous MMSE-Based OSIC detector.