An RF IC for a 1.1-V VHF paging receiver is developed. In order to reduce the number of components, it employs direct-conversion frequency shift keying (FSK) architecture. The RF IC adopts two new gain control circuits so as to achieve a wide input dynamic range with only a 1.1 V power supply. One is a low-voltage, low-noise, low-distortion RF amplifier and the other is a low-voltage AGC amplifier. By applying these new circuit technologies, the RF IC achieves a voltage gain of 50.5 dB and a noise figure of 4.3 dB with only 2.0 mW power consumption. Overall, the paging receiver achieves a high sensitivity of -130 dBm and low-intermodulation sensitivity of -37 dBm with bit error rate of 310-2. This paper describes the new high-frequency low-voltage circuit technologies applied in the RF IC.

A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.

This paper describes a new method for designing switching software called DDL (Data Driven Logic). The new design method adopts the dataflow concept and graphical programming using a dataflow diagram. A dataflow diagram is used for software representation, and a dataflow mechanism is emulated on a conventional von Neumann processor. The DDL method has the following advantages; (1) general advantages of dataflow software; i.e. easily understandable programs using graphical representations, and easy description of parallelism, (2) modular design using reusable software components, (3) easy design and programming with a graphical user interface. This paper presents the general concepts and structure of DDL. It also discusses the dataflow emulation mechanism, the DDL software development process, the DDL programming environment, an evaluation of the DDL call processing program applied to a commercial PABX, and some unsolved problems of DDL.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.

A process of mixing viscous fluids, such as oil-based paints is applied to generate marble patterns. It is difficult to get the exact flow function of the viscous fluid, then we express the flow in terms of velocity vectors derived from simplified flow phenomena, in which the viscous liquid is supposed to be a collection of finite liquid elements. The position change of each element is calculated as the function of time and several examples of the obtained marble patterns are illustrated.

A ner trial of statistical evaluation for a nonstationary traffic flow and its traffic noise is proposed as a prediction method of its probability distribution function by considering the temporal change of distribution parameters especially from a structural viewpoint. First, a headway distribution of the nonstationary traffic flow passing through within a road segment is proposed on the basis of an Erlang distribution by reflecting a temporal change of its distribution parameters. Then, an initial phase density concerning with asynchronous counting method and the probability of counting n cars over a long time interval are derived from the above nonstationary expression of headway distribution. Thus, the statistics of noise intensity at an observation point has been predicted by combining the above probabilistic factors and deterministic factors related to noise propagation environment with use of a compound stochastic process model. Finally, te effectivenss of the proposed theory has been confirmed experimentally by applying it to the actual traffic flow on a highway.

This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.

The inherent simplicity of the LMS (Least Mean Square) Algorithm has lead to its wide usage. However, it is well known that high speed convergence and low final misadjustment cannot be realized simultaneously by the conventional LMS method. To overcome this trade-off problem, a new adaptive algorithm using Multiple ADF's (Adaptive Digital Filters) is proposed. The proposed algorithm modifies coefficients using multiple gradient vectors of the squared error, which are computed at different points on the performance surface. First, the proposed algorithm using 2 ADF's is discussed. Simulation results show that both high speed convergence and low final misadjustment can be realized. The computation time of this proposed algorithm is nearly as much as that of LMS if parallel processing techniques are used. Moreover, the proposed algorithm using more than 2 ADF's is discussed. It is understood that if more than 2 ADF's are used, further improvement in the convergence speed in not realized, but a reduction of the final misadjustment and an improvement in the stability are realized. Finally, a method which can improve the convergence property in the presence of correlated input is discussed. It is indicated that using priori knowledge and matrix transformation, the convergence property is quite improved even when a strongly correlated signal input is applied.

In this paper, restricted overflow strategy is proposed as a novel channel access strategy for the queueable hierarchical channel structure, which has been proposed as one of "Wideband-ISDN" channel structures. In this policy, overflow from higher bit rate channels to lower bit rate channels is partly restricted by the number of waiting customers in the higher channel's buffer. Therefore, thresholds, which restrict overflow, are considered on the buffer. First, we present the system model with two types of services and restricted overflow strategy. Next, we provide a queueing analysis of this strategy. After that, some numerical results of both conventional overflow strategy and restricted overflow strategy are presented, and we compare the average holding times under these strategies. Finally, we show that, if we choose appropriate thresholds, the average holding time of higher level traffic is improved.

Based on the Fornasini-Marchesini second local state-space (LSS) model, the coefficient sensitivities of two-dimensional (2-D) digital filters are analyzed in conjunction with frequency weighting functions. The overall sensitivity called the frequency-weighting sensitivity is then evaluated using the 2-D generalized Gramians that are newly introduced for the Fornasini-Marchesini second LSS model. Next, the 2-D filter structures that minimize the frequency-weighting sensitivity are synthesized for two cases of no constraint and scaling constraints on the state variables. Finally, an example is given to illustrate the utility of the proposed technique.

The motion of particles in low-pressure chemical vapor deposition (LPCVD) (0.4 Torr) equipment has been investigated by a numerical simulation. The effects of wafer orientation, electrostatic forces, and thermophoresis were evaluated. Horizontal surface-down processing and vertical processing can reduce particulate contamination remarkably compared with horizontal surface-up processing. Static electricity control is essential. Weakly charged wafers (several V to several 10 V) can significantly increase submicron particle deposition. In the absence of electrical forces, thermophoresis prevents deposition of particles in the size range 0.03 µmDp0.6 µm, when the temperature difference between the wafer surface and the gas inlet temperature exceeds 100. Deposition of particles smaller than 0.03 µm still occurs by diffusion.

Location theory on networks is concerned with the problem of selecting the best location in a specified network for facilities. Many studies for the theory have been done. However, few studies treat location problems on networks from the standpoint of measuring the closeness between two vertices by the capacity (maximum flow value) between two vertices. This paper concerns location problems, called covering problems on flow networks. We define two types of covering problems on flow networks. We show that covering problems on undirected flow networks and a covering problem on directed flow networks are solved in polynomial times.

Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n+-InGaAs/n+-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.

This paper proposes three configurations of slow-wave transmission lines for MMICs, i.e., double crosstie slow-wave transmission line (DCT-SLW), meander-like DCT-SLW and lumped DCT-SLW. The DCT-SLW is based on periodic structures and triplate structures. The meander-like DCT-SLW realizes a drastic size reduction in the DCT-SLW using a meander configuration of inductive and capacitive transmission lines. The multilayer spiral inductors are introduced to obtain high impedance characteristics of the meander section. The lumped DCT-SLW achieves a large slow-wave factor of 30. These proposed structures are analytically and experimentally investigated, and excellent performance is obtained. It is also shown that the proposed DCT-SLWs are superior to thin film microstrip (TFMS) lines with the same insertion phase, as regards size.

This paper investigates a method of dynamically adjusting inter-packet gaps in accordance with network conditions, and demonstrates that the number of dropped packets is a critical parameter for adjusting inter-packet gaps. This technique, known as rate flow control, can prevent overruns in high-speed, low-delay, low-error-rate networks.

This paper deals with the problem of assigning tasks to the processors of a multiprocessor system such that the sum of execution and communication costs is minimized. If the number of processors is two, this problem can be solved efficiently using the network flow approach pioneered by Stone. This problem is, however, known to be NP-complete in the general case, and thus intractable for systems with a large number of processors. In this paper, we propose a network flow approach for the task assignment problem in homogeneous hypercube networks, i.e., hypercube networks with functionally identical processors. The task assignment problem for an n-dimensional homogeneous hypercube network of N (=2n) processors and M tasks is first transformed into n two-terminal network flow problems, and then solved in time no worse than O(M3 log N) by applying the Goldberg-Tarjan's maximum flow algorithm on each two-terminal network flow problem.

A yellow light emitting display using neon-hydrogen-argon mixture as filling gas is presented. Strong "monochromatisation" of the emitted light is reported for the first time on the wavelength λ585.3 nm. Experimental results on the dependence of the "monochromatisation effect" is given for various pressure values and filling gas composition. It is underlined the existence of a process of selective population of the upper level 3p[1/2]0 of the transition corressponding to the wavelength 585.3 nm. The obtained results are discussed in relation with the reported results on yellow light laser in which a discharge in neon-hydrogen mixture is used for laser radiation generation at λ585.3 nm. The proposed explanation of different authors on the upper level population through radiative or dissociative recombination of neon ions is discussed and a new hypothesis is advanced for the strong monochromatisation observed in neon-hydrogen or neon-hydrogen-argon filled displays. According to this hypothesis, in the feeding process of the upper level 3p[1/2]0 are taking part the neon metastable states too. If such an assumption will come true, cyclic processes in yellow light generation might appear.

Unlike a noise removal recursive or averaging filter, this letter presents a temporal filter which attenuates temporal high frequency components and improves visual effects. Although temporal aliasing occurs, the proposed filter proceeds temporal bandlimitation not affected by them. To reduce effects caused by aliasing components, a spatial filtering which is applied along the trajectory of motion is investigated. The proposed filter presents a de-aliasing and effective bandlimiting characteristics as well as reducing of noises.