A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.

A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at Vcc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.

The state of the art of low-voltage (LV) analog circuit design techniques is reviewed, and fundamental design techniques are identified and classified as follows: 1) current-mode, 2) series-to-parallel, 3) signal range sharing, 4) dynamic bias, 5) linear bias, and 6) LV regulator. A relatively wide variety of low frequency application circuits have been developed, but future development is expected for wide-bandwidth application circuits such as a voltage-controlled-oscillator (VCO), a balanced multiplier, etc. The circuit techniques such as current-mode, signal range sharing, and dynamic bias will probably be most important for advanced future circuit designs.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

This paper describes an optimal scheduling approach which finds the scheduling result of the minimum functional unit cost under the given timing constraint. In this method, a well-defined search space is constructed incrementally and traversed in a branch-and-bound manner. During the traversal, tighter lower bounds are estimated and utilized coupled with the upper bound on the optimal solution in pruning the search space effectively. This method is extended to support multi-cycling operations, operation chaining, pipelined functional units, and pipelined data paths. Experimental results on some benchmarks show the efficiency of the proposed approach.

A flexible and low-cost menagement technology is desired for fabrication line of both ASICs and cutting edge LSIs. To meet such desire, a management technology named "super operator shifts" has been proposed. After taking operator's skill level into consideration, an ASIC line manager can stretch line working time by use of the super operator shifts. It results that he can successfully get 3-shifts turn around time for severe-delivery-date lots with a payment equal to about 2-shifts line-cost.

We propose a method for configuring LSI manufacturing lines so that they can not only be used to manufacture low-cost LSIs in bulk quantities but also can be used to manufacture small lots with ultra-short TAT. This is achieved by adding a relatively small amount of single-wafer processing equipment to a existing conventional processing line, and therefore involves minimum investment.

An ultra low noise 50-GHz-Band amplifier (LNA) MMIC has been developed using an AlGaAs/InGaAs pseudomorphic HEMT. A noise figure of 1.8 dB with an associated gain of 8.1 dB is achieved at 50 GHz. The noise figure is less than 2.0 dB from 50 GHz to 52.5 GHz. This is the state-of-the-art noise figure for low noise amplifiers around 50 GHz. The success of this LNA development came from the excellent HEMT and MMIC technologies and the accurate modeling of active and passive elements. Good agreement between measured and simulated data over the band from 40 GHz to 60 GHz is obtained.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

On mutually coupling lines, the transmission signal is dispersively propagated by crosstalk coupling between lines and shows complex propagation characteristics caused by reciprocal reflections. Usually, the differential equation and the integral equation have been applied to analyze the solutions of transmission lines. In this paper, we propose a different analytical method of the propagation characteristics of signal and crosstalk noise. By setting up crosstalk coupling line as a sectionally divided digital transmission network and by using the signal flow graph and the difference equation, the propagation characteristics in the frequency domain, the space domain and the time domain on mutually coupling lines can be obtained. To verify the validity of this method and analyze the complex propagation problems, we first study the crosstalk characteristics of a twisted pair cable via the third circuit by unidirectional coupling. Subsequently we will analyze the coupling theory of bidirectional coupling lines.

Self-aligned InP/InGaAs heterojunction bipolar transistors (HBTs) were fabricated with emitter electrodes of 12, 22, 25, and 220 µm2 on the same wafer to investigate the influence of lateral scaling on device performance. DC characterization of these devices showed that InP/InGaAs HBTs are less subject to the emitter-size effect than GaAs-based HBTs. Common-emitter current gain β of the smallest 12-µm2 transistor was approximately 60 which is high enough for practical use. High-frequency characteristics of the transistors were almost the same in spite of the large difference in device size. Unity current-gain cutoff frequency fT of the smallest 12-µm2 transistor was as high as 163 GHz at a collector current of 2.3 mA, which ranks with the fT176 GHz achieved by the largest 220-µm2 transistor at a collector current of 45 mA. The smallest device also showed an excellent high-speed performance of fT100 GHz at submilliampere collector currents of Ic0.6 mA. The results indicate that small-lateral-dimension InP/InGaAs HBTs are applicable to high-speed ICs with low power dissipation.

This paper proposes a constructive linearization method for transistor circuits based on a polynomial representation of nonlinear transfer functions. The nonlinear transfer functions for various configurations have been shown in a polynomial form. Then the results have been applied to several bipolar transistor circuits to exemplify the proposed designing method.

Self-modelocking of Ti:sapphire laser has obtained with less than 2 W of argon-ion laser pumping. Two independent lasers with 36 fsec and 63 fsec in pulse duration were operated by a 6 W pump laser. In the low-threshold lasers, not only an ordinary mode-locking but also a double-pulse mode-locking, where two pulses circulating in the cavity, was stable.

Mobile communication networks need public key cryptosystems that offer both low computation cost and user authentication. Tatebayashi et al. showed a key distribution protocol for such networks at Crypto'89 based on low exponent RSA. This paper shows that their protocol is not secure. We also present two types of secure and efficient key distribution protocols.

Laser diodes for optical interconnections are ideally high speed, work over a wide temperature range, and are simple to bias. This paper reports high bit-rate modulation with nearly zero bias with very low threshold 1.3µm-wavelength laser diodes over a wide temperature range. At the high temperature of 80, lasing delay was 165 ps with nearly zero bias. We demonstrated 2.5 Gbit/s modulation over a wide temperature range. Eye opening was over 34% of one time slot.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.