This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

Millimeter-wave monolithic low noise amplifier modules using 0.15 µm AlGaAs/InGaAs/GaAs pseudomorphic HEMTs have been developed at V- and W-bands for the Advanced Microwave Scanning Radiometer. To achieve low noise and high gain of V-band single-stage and W-band two-stage monolithic amplifiers, a reactive matching method is employed in the design of input noise matching and output gain matching circuits based on the results of on-carrier S-parameter measurements up to 50 GHz and noise parameter measurements at 60 and 90 GHz. A V-band four-stage monolithic amplifier module has been mounted on a hermetically-sealed package with microstrip interface and has achieved a noise figure of 3 dB with a gain of 42.2 dB at 51 GHz. A W-band six-stage amplifier module has been mounted on a hermetically-sealed package with waveguide interface and has achieved a noise figure of 4.3 dB with a gain of 28.1 dB at 91 GHz. These results represent the best noise figure performance ever achieved by multi-stage monolithic low-noise amplifier modules.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

A 0.15 µm T-shaped gate AlInAs/InGaAs high electron mobility transistor (HEMT) with an excellent RF performance has been developed using selective wet gate recess etching. The gate recess is formed by a pH-adjusted citric acid/NH4OH/H2O2 mixture with an etching selectivity of more than 30 for InGaAs over AlInAs. The standard deviation of saturation drain current (Idss) is as small as 3.2 mA for an average Idss of 47 mA on a 3 inch diameter InP wafer. The etching time for recess formation is optimized and an ft of 130 GHz and an MSG of 10 dB at 60 GHz are obtained. The extremely low minimum noise figure (Fmin) of 0.9 dB with an associated gain (Ga) of 7.0 dB has been achieved at 60 GHz for a SiON-passivated device. This noise performance is comparable to the lowest value of Fmin ever reported for an AlInAs/InGaAs HEMT with a passivation film.

The traceability of data flow diagrams against structure charts is very important for large software development. Specifying if there is a relationship between a data flow diagram and a structure chart is a time consuming task. Existing CASE tools provide a way to maintain traceability. If we can extract the input-output relationship of a system from a structure chart, the corresponding data flow diagram can be automatically generated from the relationship. For example, Benedusi et al. proposed a reverse engineering methodology to reconstruct a data flow diagram from existing code. The methodology develops a hierarchical data flow diagram from dependency relationships between the program variables. The methodology, however, transforms each module in structure charts into a process in data flow diagrams. The reconstructed diagrams may have different processes with the same name. This paper proposes a transformation algorithm that solves these problems. It analyzes the structure charts and extracts the input and ouput relationships, then determines how the set of outputs depends on the set of inputs for the data flow diagram process. After that, it produces a data flow diagram based on the include operation between the sets of output items. The major characteristics of the algorithm are that it is simple, because it only uses the basic operations of sets, it generates data flow diagrams with deterministic steps, and it can generate minimal data flow diagrams. This process will reduce the cost of traceability between data flow diagrams and structure charts.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

Data flow is a paradigm for concurrent computations in which a collection of parallel processes communicate asynchronously. For nondeterministic data flow networks many semantic models have been defined, however, it is complex to reason about the semantics of a network. In this paper, we introduce a transformation between data flow networks and the LOTOS specification language to make available theories and tools developed for process algebras for the semantic analysis based on traces of the networks. The transformation does not establish a one-to-one mapping between the traces of a data flow network and the LOTOS specification, but maps each network in a specification which usually contains more traces. The obtained system specification has the same set of traces as the corresponding network if they are finite, otherwise also non fair traces are included. Formal analysis and verification methods can still be applied to prove properties of the original data flow network, allowing in case of networks with finite traces to prove also network equivalence.

A full confocal Gaussian beam open resonator system that determines the dielectric properties of low-loss materials in the 60-GHz band is developed. To achieve high Q values a quasi-optical coupling method is used to feed the resonator. It is connected to a computer-controlled HP 8510C vector network analyzer for automatic measurement. The frequency variation method is used and the data are processed using the open resonator scalar theory. Results from 96% and 99.5% alumina samples with thicknesses ranging from 0.38 mm to 1 mm, are presented in the V band, with loss tangent values of the order of 100 µ radians. This system should be able to measure substrates as thin as less than 0.1 mm to 0.3 mm, which are the thicknesses of substrates in practical use.

This paper describes modifications to a previously proposed 8-kb/s 4-ms-delay CELP speech coding algorithm with a view to improving the speech quality while maintaining low delay and only moderately increasing complexity. The modifications are intended to improve the effectiveness of interframe pitch lag prediction and the sub-optimality level of the excitation coding to the backward adapted synthesis filter by using delayed decision and joint optimization techniques. Results of subjective listening tests using Japanese speech indicate that the coded speech quality is significantly superior to that of the 8-kb/s VSELP coder which has a 20-ms delay. A method that reduces the computational complexity of closed-loop 3-tap pitch prediction with no perceptible degradation in speech quality is proposed, based on representing the pitch-tap vector as the product of a scalar pitch gain and a normalized shape codevector.

Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The Vt shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.

MRI is a widely used diagnostic imaging modality because it has excellent diagnostic capabilities, is safe to use and generates images not affected by bone artifacts. Images are obtained by utilizing the phenomenon of Nuclear Magnetic Resonance (NMR) by which protons located in a static magnetic field absorb radiofrequency (RF) pulses with a specific frequency and release a part of the energy as a NMR signal. Potentially MRI has the ability to provide functional and metabolic information (such as flow, temperature, diffusion, neuron activity) in addition to morphological information. This paper describes the imaging principles and provides a general outline of some applications: flow imaging, metabolite imaging and temperature imaging.

A bipolar low-voltage multiplier core is presented. The proposed low-voltage multiplier core is built from a bipolar quadritail cell. Voltages applied to the individual bases of the transistors in the bipolar quadritail cell are aVxbVy, (a1)Vx(b1)Vy ,aVx(b1)Vy, and (a1)VxbVy, where Vx and Vy are the input signals, and a and b are constants, for example, VxVy, O, Vx, and Vy. Simple input systems using resistive dividers are also described. The dc transfer characteristics were verified on a breadboard using transistor-arrays and discrete components. The dc transfer characteristic of the proposed multiplier core is very close to that of the Gilbert multiplier cell, but the proposed multiplier core is operable on low supply voltage. Therefore, a bipolar multiplier core using a quadritail cell is a low-voltage version of the Gilbert multiplier cell. The proposed bipolar multiplier is practically useful because it can be easily implemented in integrated circuits by utilizing a multiplier core and a resistor-only input system, and it also operates at very lowvoltage. Therefore, the proposed bipolar multipliers are very suitable for low-power operation.

The state of the art of low-voltage (LV) analog circuit design techniques is reviewed, and fundamental design techniques are identified and classified as follows: 1) current-mode, 2) series-to-parallel, 3) signal range sharing, 4) dynamic bias, 5) linear bias, and 6) LV regulator. A relatively wide variety of low frequency application circuits have been developed, but future development is expected for wide-bandwidth application circuits such as a voltage-controlled-oscillator (VCO), a balanced multiplier, etc. The circuit techniques such as current-mode, signal range sharing, and dynamic bias will probably be most important for advanced future circuit designs.

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.

Low-power technology for front-end GaAs ICs and hybrid IC (HIC) for a mobile communication equipment will be presented. For low-power operation of GaAs front-end ICs, new techniques of the intermediate tuned circuits, the single-ended mixer, dualgate MESFETs, and the asymmetric self-aligned LDD process were investigated. The designed down-converter IC showed conversion gain of 21 dB, noise figure of 3.5 dB, 3rd-order intercept point in output level (IP3out) of 4.0 dBm, image-rejection ratio of 20 dB at 880 MHz, operating at 3.0 V of supply voltage and 5.0 mA of dissipation current. The down-converter IC was also designed for 1.9 GHz to obtain conversion gain of 20 dB, noise figure of 4.0 dB, IP3out of 4.0 dBm, image-rejection ratio of 20 dB at 3.0 V, 5.0 mA. The up-converter IC was designed for 1.9 GHz using the same topology of circuit and showed conversion gain of 15 dB, IP3out of 7.5 dBm, and 1 dB compression level of -8 dBm with -20 dBm of LO input power, operating at 3.0 V, 8.0 mA. Another approach to the low-power operation was carried out by HIC using the GaAs down-converter IC chip. The HIC was designed for 880 MHz to show conversion gain of 27 dB, noise figure of 3.3 dB, IP3out of 3.0 dBm, image-rejection ratio of 12 dB, at 2.7 V, 4.5 mA. The HIC measures only 8.0 mm6.0 mm1.2 mm.

A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.