In this paper, we study three-dimensional motion estimation using optical flow. We construct a weighted quotient-form objective function that provides an unbiased estimator. Using this objective function with a certain projection operator as a weight drastically reduces the computational cost for estimation compared with using the maximum likelihood estimator. To reduce the variance of the estimator, we examine the weight, and we show by theoretical evaluations and simulations that, with an appropriate projection function, and when the noise variance is not too small, this objective function provides an estimator whose variance is smaller than that of the maximum likelihood estimator. The use of this projection is based on the knowledge that the depth function has a positive value (i. e., the object is in front of the camera) and that it is generally smooth.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.

A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 510-17 A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

Experimental demonstrations of congestion avoidance network are described. These test results show the feasibility of multi-media services in wide area networks; no congestion and fair band sharing are achieved with almost 716km optical fiber propagation delay.

This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.

A continuous-wave ultrasonic Doppler system using wide field ultrasound transducers was applied to telemeter blood velocity from the carotid artery of exercising subjects. Velocity spectrogram was obtained by Hanning windowed fast Fourier transformation of the telemetered data. Distortion caused by a high-pass filter and transducers in the telemetry system was discussed in the paper. As the maximum Reynolds number in our experiment was 1478 which is smaller than the critical level of 2000, the blood flow should be laminar. Spatial velocity profiles were then reconstructed from the velocity spectrogram. In this paper, we defined a converging index Q of the velocity spectrum to measure the bluntness of the spatial velocity distribution across the blood vessel. Greater Q, the blunter the velocity profile will be. Simulation results for spatial velocity distributions of theoretical parabolic flow and Gaussian-distribution spectra with varied Q value showed that the cut-off effect by a high-pass filter of cut-off frequency fc=200Hz in our system could be ignored when the axial velocity is larger than 0.30 m/s and Q is greater than 2.0. Our experimental results, in contrast to those obtained from phantom systems by us and by Hein and O'Brien, indicate that the distribution of blood velocity is much blunter than previously thought. The Q index exceeded 10 during systole, whereas it was 0.5 in parabolic flow. The peak of Q index lagged behind that of axial blood velocity by approximately 0.02s. The phase delay of the Q index curve might be due to the time needed for the red blood cells to form the non-homogeneous distribution.

This paper presents a new method for solving the structure-from-motion problem for optical flow. The fact that the structure-from-motion problem can be simplified by using the linearization technique is well known. However, it has been pointed out that the linearization technique reduces the accuracy of the computation. In this paper, we overcome this disadvantage by correcting the linearized solution in a statistically optimal way. Computer simulation experiments show that our method yields an unbiased estimator of the motion parameters which almost attains the theoretical bound on accuracy. Our method also enables us to evaluate the reliability of the reconstructed structure in the form of the covariance matrix. Real-image experiments are conducted to demonstrate the effectiveness of our method.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.

This paper describes a 600 mV single-chip MPEG2 video decoder, implemented in a 0.5 µm triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode the Main profile at Main level of MPEG2 bit streams.

This paper surveys trends in and prospects for low power LSI circuits technologies for portable terminal equipment, in which low-voltage operation of LSIs will be emphasized because this equipment will be battery-powered. Since this brings about serious operation speed degradation of LSIs, however, it will become more and more important how to operate them faster under low-supply voltage. We propose two new circuit techniques that make it possible to operate LSIs at high speed even when the supply voltage is very low (1-2 V corresponding to one or two battery cells). The new low-voltage RF LSI circuit technique, developed using silicon bipolar technology and using a novel current-folded mixer architecture for the modulator, result in a highly linear modulator that operates at 2 V. Its power consumption is less than 2/3 that of previously reported ICs. And for a low voltage baseband LSI we propose the multi-threshold CMOS (MTCMOS) technique, which uses two sets of threshold-voltage levels so that the LSI can operate at high speed when driven by a 1-V power supply. The multi-threshold CMOS architecture enabled us to create LSIs that operate faster than conventional CMOS circuits using high-threshold-voltage MOSFETs. When operating with a 1-V power supply, our LSIs are three times faster than the conventional ones.

In circuit partitioning for FPGAs, partitioned signal nets are connected using I/O blocks, through which signals are coming from or going to external pins. However, the number of I/O blocks per chip is relatively small compared with the number of logic-blocks, which realize logic functions, accommodated in the FPGA chip. Because of the I/O block limitation, the size of a circuit implemented on each FPGA chip is usually small, which leads to a serious decrease of logic-block utilization. It is required to utilize unused logic-blocks in terms of reducing the number of I/O blocks and realize circuits on given FPGA chips. In this paper, we propose an algorithm which partitions an initial circuit into multi-FPGA chips. The algorithm is based on recursive bi-partitioning of a circuit. In each bi-partitioning, it searches a partitioning position of a circuit such that each of partitioned subcircuits is accommodated in each FPGA chip with making the number of signal nets between chips as small as possible. Such bi-partitioning is achieved by computing a minimum cut repeatedly applying a network flow technique, and replicating logic-blocks appropriately. Since a set of logic-blocks assigned to each chip is computed separately, logic-blocks to be replicated are naturally determined. This means that the algorithm makes good use of unused logic-blocks from the viewpoint of reducing the number of signal nets between chips, i.e. the number of required I/O blocks. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with conventional algorithms.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

I have examined factors for implementing a high-speed, low-power-consumption thermal head. In conventional thermal heads, a heat insulation layer is provided between the heating resistor and the radiator. I found it desirable to implement fast operation and low power consumption to lower the thermal conductivity of the heat insulation layer and to thin the heat insulation layer. I also found there is an optimum heat characteristic to the thickness of one heat insulation layer. I assumed polyimide as a material for the heat insulation layer which could materialize the hypothesis, and studied necessary items based on the thermal calculation. I manufactured a trial thermal head on the basis of this result and confirmed that our assumptions were correct. In addition, to confirm that the assumption is also ultimately correct, I fabricated a trial thermal head only consisting of a heating resistor and without a protective coat and a heat insulation layer. I confirmed that the structure with only the heating resistor exhibited excellent heat response and consumed less power necessary for heating.

This paper presents a theoretical study on transmission properties of bent optical waveguides of uniaxial anisotropic material. The waveguiding structure consists of two parallel straight slab waveguides connecting by an oblique section. By arranging the direction of the optical axis in the oblique section so that the wave normal always points to the same direction throughout the waveguiding structure, low loss transmission can be realized. The analysis of wave propagation through the structure is based on the finite difference beam propagation method. Numerical results indicate that by optimally arranging the direction of the optical axis in the oblique section power coupling coefficients better than 95% can be obtained for any tilt angle of the oblique section when the tilt angle is smaller than 2 degrees. Some field distributions are also presented along the waveguiding structure.

This paper presents a new learning method to improve noise tolerance in Fuzzy ART. The two weight vectors: the top-down weight vector and the bottom-up weight vector are differently updated by a weighted sum and a fuzzy AND operation. This method effectively resolves the category proliferation problem without increasing the training epochs in noisy environments.

In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.