This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

COordinate Rotation DIgital Computer (CORDIC) is an efficient algorithm to compute elementary arithmetic such as trigonometric, exponent, and logarithm. However, the main drawback of the conventional CORDIC is that the number of iterations is equal to the number of angle constants. Among a great deal of research to overcome this disadvantage, angle recording method is an effective method because it is capable of reducing 50% of the number of iterations. Nevertheless, the hardware architecture of this algorithm is difficult to implement in pipeline. Therefore, a low-latency parallel pipeline hybrid adaptive CORDIC (PP-CORDIC) architecture is proposed in this paper. In the design hybrid architecture was exploited together with pipeline and parallel technique to achieve low latency. This design is able to operate at 122.6 MHz frequency and costs 8, 12, and 15 clock cycles latency in the best, average, and worst case, respectively. More significantly, the latency of PP-CORDIC in the worst case is 1.1X lower than that of the Altera's commercial floating-point sine and cosine IP cores.

The Android pattern unlock is a widely adopted graphical password system that requires a user to draw a secret pattern connecting points arranged in a grid. The theoretical security of pattern unlock can be defined by the number of possible patterns. However, only upper bounds of the number of patterns have been known except for 3×3 and 4×4 grids for which the exact number of patterns was found by brute-force enumeration. In this letter, we present the first lower bound by computing the minimum number of visible points from each point in various subgrids.

Through-silicon via (TSV) assignment problem is one of the key design challenges of 3-D IC which is crucial to the wire length and signal delay. In this work we formulate the 3-D IC TSV assignment as an Integer Minimum Cost Multi Commodity (IMCMC) problem on a IMCMC network, and propose a multi-level algorithm. It coarsens the IMCMC network level by level, applies a rough flow assignment on each level of coarsened graph, and generates only promising edges to reduce the IMCMC network size. Benefiting from the multi-level structure, we propose a mixed single and multi commodity flow method improve the TSV assignment solution quality. Moreover, given a TSV assignment, we propose an extended layer by layer algorithm to further optimize the TSV assignment. The experimental results demonstrate that our multi-level with mixed single and multi commodity flow algorithm achieves not only smaller wire length but also shorter runtime compared to other existing works.

Workflow nets (WF-nets for short) are a standard way to automate business processes. Well-Structured WF-nets (WS WF-nets for short) are an important subclass of WF-nets because they have a well-balanced capability to expression power and analysis power. In this paper, we revealed structural and behavioral properties of WS WF-nets. Our results on structural properties are: (i) There is no EFC but non-FC WF-net in WS WF-nets; (ii) A WS WF-net is sound iff it is a van Hee et al.'s ST-net. Our results on behavioral properties are: (i) Any WS WF-net is safe; (ii) Any WS WF-net is separable; (iii) A necessary and sufficient condition on reachability of sound WS WF-net (N,[pIk]). Finally we illustrated the usefulness of the proposed properties with an application example of analyzing workflow evolution.

Based on the codewords of the [q,2,q-1] extended Reed-Solomon (RS) code over the finite field Fq, we can construct a regular binary γq×q2 matrix H(γ,q), where q is a power of 2 and γ≤q. The matrix H(γ,q) defines a regular low-density parity-check (LDPC) code C(γ,q), called a full-length RS-LDPC code. Using some analytical methods, we completely determine the values of s(H(4,q)), s(H(5,q)), and d(C(5,q)) in this letter, where s(H(γ,q)) and d(C(γ,q)) are the stopping distance of H(γ,q) and the minimum distance of C(γ,q), respectively.

We integrate a pressure sensing capacitor and a low operation voltage OFET to develop a pressure sensor. The OFET was used as a readout device and an external pressure was loaded on the sensing capacitor. The OFET operates at less than 5 V and the change in the drain current in response to the pressure load (100 kPa) is two orders of magnitude.

Contact lubricants have been used in electric contacts such as connectors. Contact failures for down size of connector contacts with low contact force and cost down of gold plated are a serious problem to be solved. One solution is the application of lubricants to the contacts. Particularly these contacts are exposed to elevated temperature under reflow treatment in assembling processes. It is an important subject should be clarified that the deterioration phenomenon of increases in contact resistance properties under the reflow. This degradation should be induced by two causes. Namely, one is a surface contamination due to oxidation of diffused small amount of additives through gold plated layer. The other is decomposition of the coated lubricants. In this study, first of all, degradation of contact resistance properties were measured, and change of images of STM for exposure time of high temperature were observed. To clarify more in detail this degradation of the contact resistance, for both clean gold plated surface and heated clean surface were examined by using XPS and AES analysis. As results, contact resistance properties of clean surface were found to degrade for exposure at the elevated temperature. This degradation was found due to oxidation of base metal nickel and cobalt additive to gold plated surface. However, influence of the contact lubrication on the degradation of contact resistance was not recognized. The change of composition of an olefin lubricant was discussed by using STM images. Moreover, growth of oxide film on the clean surface was found as cubic law by using an ellipsometry.

In this paper we use equivalent circuits to analyze the wavelengths in a Fast and Slow wave Waffle-iron Ridge Guide (FS-WRG). An equivalent circuit for the transverse direction is employed and the transverse resonance method is used to determine the fast wave wavelength. Another equivalent circuit, for the inserted series reactance in the waveguide, is employed for the fast and slow wave wavelength. We also discuss the physical system that determines the wavelengths and the accuracy of this analysis by comparing the wavelengths with those calculated by EM-simulation. Furthermore, we demonstrate use of the results obtained in designing an array antenna.

The study focuses on the adaptation problem for HTTP low-delay live streaming over mobile networks. In this context, the client's small buffer could be easily underflown due to throughput variations. To maintain seamless streaming, we present a probabilistic approach to adaptively decide the bitrate for each video segment by taking into account the instant buffer level. The experimental results show that the proposed method can significantly reduce buffer underflows while providing high video bitrates.

In this paper, a new class of low-hit-zone (LHZ) frequency-hopping sequence sets (LHZ FHS sets) is constructed based upon the Cartesian product, and the periodic partial Hamming correlation within its LHZ are studied. Studies have shown that the new LHZ FHS sets are optimal according to the periodic partial Hamming correlation bounds of FHS set, and some known FHS sets are the special cases of this new construction.

This paper discusses a pulse generator implemented by CMOS flipped on a glass substrate aiming at low power applications with low duty cycle. The pulse generator is theoretically possible to generate a pulse at a frequency near and beyond Fmax. It also features a quick starting time and zero stand-by power. By using a simplified circuit model, analytical expressions for Q factor, energy conversion efficiency, output energy, and oscillation frequency of the pulse generator are derived. Pulse generator prototypes are designed on a 0.18 μm CMOS chip flipped over a transmission line resonator on a glass substrate. Measurement results of two different prototypes confirm the feasibility of the proposed circuit and the analytical model.

This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled architectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.

An information flow problem is a graph-theoretical formalization of the transportation of information over a complicated network. It is known that a linear network code plays an essential role in a certain type of information flow problems, but it is not understood clearly how contributing linear network codes are for other types of information flow problems. One basic problem concerning this aspect is the linear solvability of information flow problems, which is to decide if there is a linear network code that is a solution to the given information flow problem. Lehman et al. characterize the linear solvability of information flow problems in terms of constraints on the sets of source and sink nodes. As an extension of Lehman's investigation, this study introduces a hierarchy constraint of messages, and discusses the computational complexity of the linear solvability of information flow problems with the hierarchy constraints. Nine classes of problems are newly defined, and classified to one of three categories that were discovered by Lehman et al.

In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.

We treat lossless fixed-to-variable length source coding under general sources for finite block length setting. We evaluate the threshold of the overflow probability for prefix and non-prefix codes in terms of the smooth max-entropy. We clarify the difference of the thresholds between prefix and non-prefix codes for finite block length. Further, we discuss our results under the asymptotic block length setting.

In this paper, an analysis of the basic process of a class of interactive-graph-cut-based image segmentation algorithms indicates that it is unnecessary to construct n-links for all adjacent pixel nodes of an image before calculating the maximum flow and the minimal cuts. There are many pixel nodes for which it is not necessary to construct n-links at all. Based on this, we propose a new algorithm for the dynamic construction of all necessary n-links that connect the pixel nodes explored by the maximum flow algorithm. These n-links are constructed dynamically and without redundancy during the process of calculating the maximum flow. The Berkeley segmentation dataset benchmark is used to prove that this method can reduce the average running time of segmentation algorithms on the premise of correct segmentation results. This improvement can also be applied to any segmentation algorithm based on graph cuts.

This paper presents a fully integrated voltage boost converter consisting of a charge pump (CP) and maximum power point tracking (MPPT) controller for ultra-low power energy harvesting. The converter is based on a conventional CP circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient charge transfer operation. The MPPT controller we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73% power conversion efficiency when the output power was 348µW. The circuit can operate at an extremely low input voltage of 0.21V.

In this paper, we propose a fast Maximal Empty Rectangle (MER) enumeration algorithm for online task placement on reconfigurable Field-Programmable Gate Arrays (FPGAs). On the assumption that each task utilizes rectangle-shaped resources, the proposed algorithm can manage the free space on FPGAs by an MER list. When assigning or removing a task, a series of MERs are selected and cut into segments according to the task and its assignment location. By processing these segments, the MER list can be updated quickly with low memory consumption. Under the proof of the upper limit of the number of the MERs on the FPGA, we analyze both the time and space complexity of the proposed algorithm. The efficiency of the proposed algorithm is verified by experiments.

This paper presents a low power millimeter-wave oscillator consisting of a current-reused topology and buffer-feedback. By connecting a buffer-feedback topology between the core LC-tank of the oscillator and the output buffer stage, the simulated oscillation frequency of the proposed oscillator is increased by 17%, compared to that of the conventional current-reused oscillator. In addition, to obtain the same output power, the proposed oscillator reduces the power dissipation by 47%, compared to that of the conventional buffer-feedback oscillator. The prototype of the proposed oscillator is fabricated in a 65nm CMOS technology with a size of 700µm×480µm including pad. Measurement results indicate an oscillation frequency of 71.3GHz, while dissipating 10mA from a 1.6V supply.