An energy-efficient nonvolatile FPGA with assuring highly-reliable backup operation using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 66% in comparison with that of a conventional worst-case-based approach where the long time write current pulse is used for the reliable write.

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators have been studied. This paper presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance.

Hybrid analog/digital precoding has attracted growing attention for millimeter wave (mmWave) communications, since it can support multi-stream data transmission with limited hardware cost. A main challenge in implementing hybrid precoding is that the channels will exhibit frequency-selective fading due to the large bandwidth. To this end, we propose a practical hybrid precoding scheme with finite-resolution phase shifters by leveraging the correlation among the subchannels. Furthermore, we utilize the sparse feature of the mmWave channels to design a low-complexity algorithm to realize the proposed hybrid precoding, which can avoid the complication of the high-dimensionality eigenvalue decomposition. Simulation results show that the proposed hybrid precoding can approach the performance of unconstrained fully-digital precoding but with low hardware cost and computational complexity.

In this letter, we focus on a system where N sources send n ≤ N different packets to one destination, through M ≥ N relays. Each relay employs random linear network coding to encode the packets it received by randomly choosing coefficients in a finite field Fq, then forwards it to the destination. Owing to the inherent errorprone nature of erasure channels, data packets received by the relay and the destination nodes may not be correct. We analyze the optimal throughput with respect to n, given a series of parameters and derive the upper and lower bounds of throughput performance. We also analyze the impact of the number of relays and the erasure probability on the throughput performance. Simulation results are well matched with the theoretical analysis.

Linear phase maximally flat digital differentiators (DDs) with stopbands obtained by minimizing the Lp norm are filters with important practical applications, as they can differentiate input signals without distortion. Stopbands designed by minimizing the Lp norm can be used to control the relationship between the steepness in the transition band and the ripple scale. However, linear phase DDs are unsuitable for real-time processing because each group delay is half of the filter order. In this paper, we proposed a design method for a low-delay maximally flat low-pass/band-pass FIR DDs with stopbands obtained by minimizing the Lp norm. The proposed DDs have low-delay characteristics that approximate the linear phase characteristics only in the passband. The proposed transfer function is composed of two functions, one with flat characteristics in the passband and one that ensures the transfer function has Lp approximated characteristics in the stopband. In the optimization of the latter function, Newton's method is employed.

Subspace representation model is an important subset of visual tracking algorithms. Compared with models performed on the original data space, subspace representation model can effectively reduce the computational complexity, and filter out high dimensional noises. However, for some complicated situations, e.g., dramatic illumination changing, large area of occlusion and abrupt object drifting, traditional subspace representation models may fail to handle the visual tracking task. In this paper, we propose a novel subspace representation algorithm for robust visual tracking by using low-rank representation with graph constraints (LRGC). Low-rank representation has been well-known for its superiority of handling corrupted samples, and graph constraint is flexible to characterize sample relationship. In this paper, we aim to exploit benefits from both low-rank representation and graph constraint, and deploy it to handle challenging visual tracking problems. Specifically, we first propose a novel graph structure to characterize the relationship of target object in different observation states. Then we learn a subspace by jointly optimizing low-rank representation and graph embedding in a unified framework. Finally, the learned subspace is embedded into a Bayesian inference framework by using the dynamical model and the observation model. Experiments on several video benchmarks demonstrate that our algorithm performs better than traditional ones, especially in dynamically changing and drifting situations.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

In order to realize an Internet-of-Things (IoT) with tiny sensors integrated in our buildings, our clothing, and the public spaces, battery lifetime and battery size remain major challenges. Power reduction in IoT sensor nodes is determined by both sleep mode as well as active mode contributions. A power state machine, at the system level, is the key to achieve ultra-low average power consumption by alternating the system between active and sleep modes efficiently. While, power consumption in the active mode remains dominant, other power contributions like for timekeeping in standby and sleep conditions are becoming important as well. For example, non-conventional critical blocks, such as crystal oscillator (XO) and resistor-capacitor oscillator (RCO) become more crucial during the design phase. Apart from power reduction, low-voltage operation will further extend the battery life. A 2.4GHz multi-standard radio is presented, as a test case, with an average power consumption in the µW range, and state-of-the-art performance across a voltage supply range from 1.2V to 0.9V.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

We propose a statistical processing method to reduce the time of chip test of high-resolution and low-speed analog-to-digital converters (ADCs). For this kinds of ADCs, due to the influence of noise, conventional histogram or momentum method suffers from long time to collect required data for averaging. The proposed method, based on physically weighing the ADC, intending to physical weights in ADC/DAC under test. It can suppress white noise to 1/22 than conventional method in a case of 10bit binary ADC. Or it can reduce test data to 1/8 or less, which directly means to reduce measuring time to 1/8 or less. In addition, it earns complete Integrated Non-Linearity (INL) and Differential Non-linearity (DNL) even missing codes happens due to less data points. In this report, we theoretically describe how to guarantee missing codes at lacked measured data points.

An online nonnegative matrix factorization (NMF) algorithm based on recursive least squares (RLS) is described in a matrix form, and a simplified algorithm for a low-complexity calculation is developed for frame-by-frame online audio source separation system. First, the online NMF algorithm based on the RLS method is described as solving the NMF problem recursively. Next, a simplified algorithm is developed to approximate the RLS-based online NMF algorithm with low complexity. The proposed algorithm is evaluated in terms of audio source separation, and the results show that the performance of the proposed algorithms are superior to that of the conventional online NMF algorithm with significantly reduced complexity.

An output voltage-current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.

We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

In this letter, a new and accurate frequency estimation method of complex exponential signals is proposed. The proposed method divides the signal samples into several identical segments and sums up the samples belonging to the same segment respectively. Then it utilizes fast Fourier transform (FFT) algorithm with zero-padding to obtain a coarse estimation, and exploits three Fourier coefficients to interpolate a fine estimation based on least square error (LSE) criterion. Numerical results show that the proposed method can closely approach the Cramer-Rao bound (CRB) at low signal-to-noise ratios (SNRs) with different estimation ranges. Furthermore, the computational complexity of the proposed method is proportional to the estimation range, showing its practical-oriented ability. The proposed method can be useful in several applications involving carrier frequency offset (CFO) estimation for burst-mode satellite communications.

Focused on network reconnaissance, eavesdropping, and DoS attacks caused by static routing policies, this paper designs a random routing mutation architecture based on the OpenFlow protocol, which takes advantages of the global network view and centralized control in a software-defined network. An entropy matrix of network traffic characteristics is constructed by using volume measurements and characteristic measurements of network traffic. Random routing mutation is triggered according to the result of network anomaly detection, which using a wavelet transform and principal component analysis to handle the above entropy matrix for both spatial and temporal correlations. The generation of a random routing path is specified as a 0-1 knapsack problem, which is calculated using an improved ant colony algorithm. Theoretical analysis and simulation results show that the proposed method not only increases the difficulty of network reconnaissance and eavesdropping but also reduces the impact of DoS attacks on the normal communication in an SDN network.

Attaining extremely low latency service in 5G cellular networks is an important challenge in the communication research field. A higher QoS in the next-generation network could enable several unprecedented services, such as Tactile Internet, Augmented Reality, and Virtual Reality. However, these services will all need support from powerful computational resources provided through cloud computing. Unfortunately, the geolocation of cloud data centers could be insufficient to satisfy the latency aimed for in 5G networks. The physical distance between servers and users will sometimes be too great to enable quick reaction within the service time boundary. The problem of long latency resulting from long communication distances can be solved by Mobile Edge Computing (MEC), though, which places many servers along the edges of networks. MEC can provide shorter communication latency, but total latency consists of both the transmission and the processing times. Always selecting the closest edge server will lead to a longer computing latency in many cases, especially when there is a mass of users around particular edge servers. Therefore, the research studies the effects of both latencies. The communication latency is represented by hop count, and the computation latency is modeled by processor sharing (PS). An optimization model and selection policies are also proposed. Quantitative evaluations using simulations show that selecting a server according to the lowest total latency leads to the best performance, and permitting an over-latency barrier would further improve results.

Identifying IDC (Internet Data Center) IP addresses and analyzing the connection relationship of IDC could reflect the IDC network resource allocation and network layout which is helpful for IDC resource allocation optimization. Recent research mainly focuses on minimizing electricity consumption and optimizing network resource allocation based on IDC traffic behavior analysis. However, the lack of network-wide IP information from network operators has led to problems like management difficulties and unbalanced resource allocation of IDC, which are still unsolved today. In this paper, we propose a method for the IP identification and connection relationship analysis of IDC based on the flow connection behavior analysis. In our method, the frequent IP are extracted and aggregated in backbone communication network based on the traffic characteristics of IDC. After that, the connection graph of frequent IP (CGFIP) are built by analyzing the behavior of the users who visit the IDC servers, and IDC IP blocks are thus identified using CGFIP. Furthermore, the connection behavior characteristics of IDC are analyzed based on the connection graphs of IDC (CGIDC). Our findings show that the method can accurately identify the IDC IP addresses and is also capable of reflecting the relationships among IDCs effectively.

The Infrastructure-as-a-Service (IaaS) cloud is attracting applications due to the scalability, dynamic resource provision, and pay-as-you-go cost model. Scheduling scientific workflow in the IaaS cloud is faced with uncertainties like resource performance variations and unknown failures. A schedule is said to be robust if it is able to absorb some degree of the uncertainties during the workflow execution. In this paper, we propose a novel workflow scheduling algorithm called Dynamic Earliest-Finish-Time (DEFT) in the IaaS cloud improving both makespan and robustness. DEFT is a dynamic scheduling containing a set of list scheduling loops invoked when some tasks complete successfully and release resources. In each loop, unscheduled tasks are ranked, a best virtual machine (VM) with minimum estimated earliest finish time for each task is selected. A task is scheduled only when all its parents complete, and the selected best VM is ready. Intermediate data is sent from the finished task to each of its child and the selected best VM before the child is scheduled. Experiments show that DEFT can produce shorter makespans with larger robustness than existing typical list and dynamic scheduling algorithms in the IaaS cloud.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.