This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

This paper proposes and demonstrates a 65nm CMOS process cascode single-inductor-dual-output (SIDO) boost converter whose outputs are Li-ion battery and 1V low voltage supply for RF wireless power transfer (WPT) receiver. The 1V power supply is used for internal control circuits to reduce power consumption. In order to withstand 4.2V Li-ion battery output, cascode 2.5V I/O PFETs are used at the power stage. On the other hand, to generate 1V while maintaining 4.2V tolerance at 1V output, cascode 2.5V I/O NFETs output stage is proposed. Measurement results show conversion efficiency of 87% at PIN=7mW, ILOAD=1.6mA and VBAT=4.0V, and 89% at PIN=7.9mW, ILOAD=2.1mA and VBAT=3.4V.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

This paper proposes an ultra-low quiescent current low-dropout regulator (LDO) with a flipped voltage follower (FVF)-based load transient enhanced circuit for wireless sensor network (WSN). Some characteristics of an FVF are low output impedance, low voltage operation, and simple circuit configuration [1]. In this paper, we focus on the characteristics of low output impedance and low quiescent current. A load transient enhanced circuit based on an FVF circuit configuration for an LDO was designed in this study. The proposed LDO, including the new circuit, was fabricated in a 0.6 µm CMOS process. The designed LDO achieved an undershoot of 75 mV under experimental conditions of a large load transient of 100 µA to 10 mA and a current slew rate (SR) of 1 µs. The quiescent current consumed by the LDO at no load operation was 204 nA.

Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.

In the age of big data, recommendation systems provide users with fast access to interesting information, resulting to a significant commercial value. However, the extreme sparseness of user assessment data is one of the key factors that lead to the poor performance of recommendation algorithms. To address this problem, we propose a spectral clustering recommendation scheme with low-rank matrix completion and spectral clustering. Our scheme exploits spectral clustering to achieve the division of a similar user group. Meanwhile, the low-rank matrix completion is used to effectively predict un-rated items in the sub-matrix of the spectral clustering. With the real dataset experiment, the results show that our proposed scheme can effectively improve the prediction accuracy of un-rated items.

In IoT (Internet-of-Things) era, the number and variety of hardware devices becomes continuously increasing. Several IoT devices are utilized at infrastructure equipments. How to maintain such IoT devices is a serious concern. Capacitance measurement is one of the powerful ways to detect anomalous states in the structure of the hardware devices. Particularly, measuring capacitance while the hardware device is running is a major challenge but no such researches proposed so far. This paper proposes a capacitance measuring device which measures device capacitance in operation. We firstly combine the AC (alternating current) voltage signal with the DC (direct current) supply voltage signal and generates the fluctuating signal. We supply the fluctuating signal to the target device instead of supplying the DC supply voltage. By effectively filtering the observed current in the target device, the filtered current can be proportional to the capacitance value and thus we can measure the target device capacitance even when it is running. We have implemented the proposed capacitance measuring device on the printed wiring board with the size of 95mm × 70mm and evaluated power consumption and accuracy of the capacitance measurement. The experimental results demonstrate that power consumption of the proposed capacitance measuring device is reduced by 65% in low-power mode from measuring mode and proposed device successfully measured capacitance in 0.002μF resolution.

Matching circuits using LC elements are widely applied to high-frequency circuits such as power amplifier (PA) and low-noise amplifier (LNA). For determining matching condition of multi-stage matching circuits, this paper shows that any multi-stage LC-Ladder matching circuit with resistive termination can be decomposed to the extended L-type matching circuits with resistive termination containing negative elements where the analytical solution exists. The matching conditions of each extended L-type matching circuit are obtained easily from the termination resistances and the design frequency. By synthesizing these simple analysis solutions, it is possible to systematically determine the solution even in a large number of stages (high order) matching circuits.

A low frequency electric field probe that integrates data acquisition and storage is developed in this paper. An electric small monopole antenna printed on the circuit board is used as the receiving antenna; the rear end of the monopole antenna is connected to the integral circuit to achieve the flat frequency response; the logarithmic detection method is applied to obtain a high measurement dynamic range. In addition, a Microprogrammed Control Unit is set inside to realize data acquisition and storage. The size of the probe developed is not exceeding 20 mm × 20 mm × 30 mm. The field strength 0.2 V/m ~ 261 V/m can be measured in the frequency range of 500 Hz ~ 10 MHz, achieving a dynamic range over 62 dB. It is suitable for low frequency electric field strength measurement and shielding effectiveness test of small shield.

This paper presents on-wafer noise figure (NF) de-embedding method of differential low noise amplifier (LNA). The characterization of NF was set up and referred as multi-stage network. The Friis law was applied to improve from the noise contributions from the subsequent stages. The correlated differential NF is accurately obtained after de-embedding the noise contribution from the interconnections and external components. Details of equations and measurement procedure are reported in this work. A 2.4GHz differential LNA was tested to demonstrate the feasibility of measurement and showed precise NF compared with other methods. The result shows an NF of 0.57dB achieved using de-embedding method and 1.06dB obtained without the de-embedding method. This is an improvement of 0.49dB of NF measurement.

A triple-band CP rectenna for ambient RF energy harvesting is presented in this paper. A simple broadband CP slot antenna has been proposed with the bandwidth of 51.1% operating from 1.53 to 2.58GHz, which can cover GSM-1800, UMTS-2100 and 2.45GHz WLAN bands. Accordingly, a triple-band rectifying circuit is designed to convert RF energy in the above bands, with the maximum RF-DC conversion efficiency of 42.5% at a relatively low input power of -5dBm. Additionally, the rectenna achieves the maximum conversion efficiency of 12.7% in the laboratory measurements. The measured results show a good performance in the laboratory measurements.

In this letter, we propose a more secure modeling and simulation approach that can systematically detect state variable corruptions caused by buffer overflows in simulation models. Using our approach, developers may not consider secure coding practices related to the corruptions. We have implemented a prototype of the approach based on a modeling and simulation formalism and an open source simulator. Through optimization, the prototype could show better performance, compared to the original simulator, and detect state variable corruptions.

We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

High frame rate and ultra-low delay are the most essential requirements for building excellent human-machine-interaction systems. As a state-of-the-art local keypoint detection and feature extraction algorithm, A-KAZE shows high accuracy and robustness. Nonlinear scale space is one of the most important modules in A-KAZE, but it not only has at least one frame delay and but also is not hardware friendly. This paper proposes a hardware oriented nonlinear scale space for high frame rate and ultra-low delay A-KAZE matching system. In the proposed matching system, one part of nonlinear scale space is temporally forward and calculated in the previous frame (proposal #1), so that the processing delay is reduced to be less than 1 ms. To improve the matching accuracy affected by proposal #1, pre-adjustment of nonlinear scale (proposal #2) is proposed. Previous two frames are used to do motion estimation to predict the motion vector between previous frame and current frame. For further improvement of matching accuracy, pixel-level pre-adjustment (proposal #3) is proposed. The pre-adjustment changes from block-level to pixel-level, each pixel is assigned an unique motion vector. Experimental results prove that the proposed matching system shows average matching accuracy higher than 95% which is 5.88% higher than the existing high frame rate and ultra-low delay matching system. As for hardware performance, the proposed matching system processes VGA videos (640×480 pixels/frame) at the speed of 784 frame/second (fps) with a delay of 0.978 ms/frame.

High frame rate and ultra-low delay matching system plays an increasingly important role in human-machine interactions, because it guarantees high-quality experiences for users. Existing image matching algorithms always generate mismatches which heavily weaken the performance the human-machine-interactive systems. Although many mismatch removal algorithms have been proposed, few of them achieve real-time speed with high frame rate and low delay, because of complicated arithmetic operations and iterations. This paper proposes a temporal constraints and block weighting judgement based high frame rate and ultra-low delay mismatch removal system. The proposed method is based on two temporal constraints (proposal #1 and proposal #2) to firstly find some true matches, and uses these true matches to generate block weighting (proposal #3). Proposal #1 finds out some correct matches through checking a triangle route formed by three adjacent frames. Proposal #2 further reduces mismatch risk by adding one more time of matching with opposite matching direction. Finally, proposal #3 distinguishes the unverified matches to be correct or incorrect through weighting of each block. Software experiments show that the proposed mismatch removal system achieves state-of-the-art accuracy in mismatch removal. Hardware experiments indicate that the designed image processing core successfully achieves real-time processing of 784fps VGA (640×480 pixels/frame) video on field programmable gate array (FPGA), with a delay of 0.858 ms/frame.

This paper proposes a successive interference cancellation (SIC) of independent component analysis (ICA) aided spatial division multiple access (SDMA) for Gaussian filtered frequency shift keying (GFSK) in Bluetooth low energy (BLE) systems. The typical SDMA scheme requires estimations of channel state information (CSI) using orthogonal pilot sequences. However, the orthogonal pilot is not embedded in the BLE packet. This fact motivates us to add ICA detector into BLE systems. In this paper, focusing on the covariance matrix of ICA outputs, SIC can be applied with Cholesky decomposition. Then, in order to address the phase ambiguity problems created by the ICA process, we propose a differential detection scheme based on the MAP algorithm. In practical scenarios, it is subject to carrier frequency offset (CFO) as well as symbol timing offset (STO) induced by the hardware impairments present in the BLE peripherals. The packet error rate (PER) performance is evaluated by computer simulations when BLE peripherals simultaneously communicate in the presence of CFO and STO.

A fully integrated 16-phase 8-branch Dickson charge pump is proposed and implemented to decrease the power dissipation due to parasitic capacitance at the bottom plate of the boost capacitor. By using the charge recycling concept, 87% of the power consumption related to parasitic capacitance is saved. In a 4-stage version of this charge pump, a maximum power efficiency of 41% is achieved at 35µA output current and 11V output voltage from a 3.3V supply voltage. The proposed multi-branch charge pump can also reach a very low output voltage ripple of only 0.146% at a load resistance of 1MΩ, which is attributed to the fact that the 8-branch charge pump can transfer charges to the output node eight times consecutively during one clock period. In addition, a high voltage gain of 4.6 is achieved in the 4-stage charge pump at light load conditions. The total chip area is 0.57mm2 in a 0.35µm HV CMOS technology.

Addition is a key fundamental function for many error-tolerant applications. Approximate addition is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a conventional ripple carry adder and a conventional carry look-ahead adder, the proposed 16-bit adder reduced the power consumption by 54.1% and 57.5%, respectively, and the critical path delay by 72.5% and 54.2%, respectively. In addition, results from an image processing application indicate that the quality of processed images can be controlled by the proposed adder. Good scalability of the proposed adder is demonstrated from the evaluation results using a 32-bit length.

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

We propose the design method of a compact long-wavelength-pass filter implemented in a two-dimensional metal-dielectric-metal (MDM) waveguide with three stubs using a transmission line model based on a low-pass prototype filter, and present the wavelength characteristics for filters in an MDM waveguide based on 0.5- and 3.0-dB equal-ripple low-pass prototype filters.