The paper presents a low power, wideband operational trans-conductance amplifier (OTA) for applications to drive large capacitive loads. In order to satisfy the low static power dissipation, high-speed, while reserving high current driving capability, the complementary slew-rate enhancer in conjunction with a dual class AB input stage to improve the slew-rate of a rail-to-rail two-stage OTA is proposed. The proposed architecture was implemented using 0.5µm CMOS process with a supply voltage of 5V. The slew-rate can achieve 68V/µsec at static power dissipation of 0.9mW, which can be used to efficiently drive larger than 6 nF capacitive load. The measured output has a total harmonic distortion of less than 5%.

The flexibility of wireless communication makes it more and more widely used in industrial scenarios. To satisfy the strict real-time requirements of industry, various wireless methods especially based on the time division multiple access protocol have been introduced. In this work, we first conduct a mathematical analysis of the network model and the problem of minimum packet loss. Then, an optimal Real-time Scheduling algorithm based on Backtracking method (RSBT) for industrial wireless sensor networks is proposed; this yields a scheduling scheme that can achieve the lowest network packet loss rate. We also propose a suboptimal Real-time Scheduling algorithm based on Urgency and Concurrency (RSUC). Simulation results show that the proposed algorithms effectively reduce the rate of the network packet loss and the average response time of data flows. The real-time performance of the RSUC algorithm is close to optimal, which confirms the computation efficiency of the algorithm.

High frame rate and ultra-low delay matching system plays an important role in various human-machine interactive applications, which demands better performance in matching deformable and out-of-plane rotating objects. Although many algorithms have been proposed for deformation tracking and matching, few of them are suitable for hardware implementation due to complicated operations and large time consumption. This paper proposes a hardware-oriented template update and recovery method for high frame rate and ultra-low delay deformation matching system. In the proposed method, the new template is generated in real time by partially updating the template descriptor and adding new keypoints simultaneously with the matching process in pixels (proposal #1), which avoids the large inter-frame delay. The size and shape of region of interest (ROI) are made flexible and the Hamming threshold used for brute-force matching is adjusted according to pixel position and the flexible ROI (proposal #2), which solves the problem of template drift. The template is recovered by the previous one with a relative center-shifting vector when it is judged as lost via region-wise difference check (proposal #3). Evaluation results indicate that the proposed method successfully achieves the real-time processing of 784fps at the resolution of 640×480 on field-programmable gate array (FPGA), with a delay of 0.808ms/frame, as well as achieves satisfactory deformation matching results in comparison with other general methods.

We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.

The monocone antenna is a type of monopole antenna that has wideband characteristics. This paper proposes a low-profile monocone antenna with a planar inverted-F structure. The characteristics of the proposed antenna are analyzed through a simulation. The results demonstrate that the low-profile antenna offers wideband performance, and the relative bandwidth of VSWR ≤ 2 is found to be more than 190%. In addition, miniaturization of the monocone antenna is elucidated. The proposed antenna is prototyped, and the validity of the simulation is verified through measurements.

A non-photorealistic rendering method has been proposed for generating oil-film-like images from photographic images by bilateral infra-envelope filter. The conventional method has a disadvantage that it takes much time to process. We propose a method for generating oil-film-like images that can be processed faster than the conventional method. The proposed method uses an iterative process with upper and lower smoothing filters. To verify the effectiveness of the proposed method, we conduct experiments using Lenna image. As a result of the experiments, we show that the proposed method can process faster than the conventional method.

Most of latency-sensitive mobile applications depend on computational resources provided by a cloud computing service. The problem of relying on cloud computing is that, sometimes, the physical locations of cloud servers are distant from mobile users and the communication latency is long. As a result, the concept of distributed cloud service, called mobile edge computing (MEC), is being introduced in the 5G network. However, MEC can reduce only the communication latency. The computing latency in MEC must also be considered to satisfy the required total latency of services. In this research, we study the impact of both latencies in MEC architecture with regard to latency-sensitive services. We also consider a centralized model, in which we use a controller to manage flows between users and mobile edge resources to analyze MEC in a practical architecture. Simulations show that the interval and controller latency trigger some blocking and error in the system. However, the permissive system which relaxes latency constraints and chooses an edge server by the lowest total latency can improve the system performance impressively.

Sparse arrays can usually achieve larger array apertures than uniform linear arrays (ULA) with the same number of physical antennas. However, the conventional direction-of-arrival (DOA) estimation algorithms for sparse arrays usually require the spatial smoothing operation to recover the matrix rank which inevitably involves heavy computational complexity and leads to a reduction in the degrees-of-freedom (DOFs). In this paper, a low-complex DOA estimation algorithm by exploiting the discrete Fourier transform (DFT) is proposed. Firstly, the spatial spectrum of the virtual array constructed from the sparse array is established by exploiting the DFT operation. The initial DOA estimation can obtain directly by searching the peaks in the DFT spectrum. However, since the number of array antennas is finite, there exists spectrum power leakage which will cause the performance degradation. To further improve the angle resolution, an iterative process is developed to suppress the spectrum power leakage. Thus, the proposed algorithm does not require the spatial smoothing operation and the computational complexity is reduced effectively. In addition, due to the extention of DOF with the application of the sparse arrays, the proposed algorithm can resolve the underdetermined DOA estimation problems. The superiority of the proposed algorithm is demonstrated by simulation results.

A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.

We have developed the world's largest 16.7-inch hybrid in-cell touch panel. To realize the large sized in-cell touch panel, we applied a vertical Vcom system and low resistance sensor, which are JDI's original technologies. For glove touch function, we applied mutual bundled driving, which increases the signal intensity higher. The panel also has a low surface reflection, curved-shaped, and non-rectangular characteristics, which are particular requirements in the automotive market. The over 15-inch hybrid in-cell touch panel adheres to automotive quality requirements. We have also developed a force touch panel, which is a new human machine interface (HMI) based on a hybrid in-cell touch panel in automotive display. This study reports on the effect of the improvements on the in-plane variation of force touch and the value change of the force signal under different environment conditions. We also a introduce force touch implemented prototype.

With the rapid increase in IoT (Internet of Things) applications, more sensor devices, generating periodic data flows whose packets are transmitted at regular intervals, are being incorporated into WSNs (Wireless Sensor Networks). However, packet collision caused by the hidden node problem is becoming serious, particularly in large-scale multi-hop WSNs. Moreover, focusing on periodic data flows, continuous packet collisions among periodic data flows occur if the periodic packet transmission phases become synchronized. In this paper, we tackle the compounded negative effect of the hidden node problem and the continuous collision problem among periodic data flows. As this is a complex variant of the hidden node problem, there is no simple and well-studied solution. To solve this problem, we propose a new MAC layer mechanism. The proposed method predicts a future risky duration during which a collision can be caused by hidden nodes by taking into account the periodic characteristics of data packet generation. In the risky duration, each sensor node stops transmitting data packets in order to avoid collisions. To the best of our knowledge, this is the first paper that considers the compounded effect of hidden nodes and continuous collisions among periodic data flows. Other advantages of the proposed method include eliminating the need for any new control packets and it can be implemented in widely-diffused IEEE 802.11 and IEEE 802.15.4 devices.

A monocone antenna is a type of monopole antenna with wideband characteristics. In this paper, a low-profile and small monocone antenna is proposed, by loading a circular plate and three oblique short elements. The characteristics of the proposed antenna are analyzed via simulation. Consequently, a low-profile and small monocone antenna can be obtained while maintaining the wideband characteristics. The relative bandwidth of the proposed antenna (voltage standing wave ratio (VSWR) ≤ 2) is greater than 158.9%. The frequency band of digital terrestrial television broadcasting and the mobile communication systems (from 470 to 3600MHz) in Japan can be completely covered with VSWR ≤ 2. In addition, the radiation patterns of the proposed antenna are omni-directional. The proposed antenna is prototyped, and the validity of the simulation is verified through measurement.

In this paper, we proposed low power consumption ASK transmitter based on the direct modulated oscillator at 60GHz-band. To achieve the proposed transmitter, high power-efficient oscillator and loss less modulator are designed. Moreover combined on-chip resonator and antenna to remove the buffer amplifier of the transmitter to reduce the power consumption and size. The proposed transmitter has been fabricated in standard 65nm CMOS process. The core area is 1130µm×590µm with pads. The operation frequency is 60.4GHz. The BER of 10^-6 is achieved under 50Mbps with power consumption of less than 260µW including the buffer amplifier. Using the proposed combined on-chip resonator and antenna, which need no buffer amplifier for transmitter and the power consumption is reduced to 180µW.

A program is non-interferent if it leaks no secret information to an observable output. However, non-interference is too strict in many practical cases and quantitative information flow (QIF) has been proposed and studied in depth. Originally, QIF is defined as the average of leakage amount of secret information over all executions of a program. However, a vulnerable program that has executions leaking the whole secret but has the small average leakage could be considered as secure. This counter-intuition raises a need for a new definition of information leakage of a particular run, i.e., dynamic leakage. As discussed in [5], entropy-based definitions do not work well for quantifying information leakage dynamically; Belief-based definition on the other hand is appropriate for deterministic programs, however, it is not appropriate for probabilistic ones.In this paper, we propose new simple notions of dynamic leakage based on entropy which are compatible with existing QIF definitions for deterministic programs, and yet reasonable for probabilistic programs in the sense of [5]. We also investigated the complexity of computing the proposed dynamic leakage for three classes of Boolean programs. We also implemented a tool for QIF calculation using model counting tools for Boolean formulae. Experimental results on popular benchmarks of QIF research show the flexibility of our framework. Finally, we discuss the improvement of performance and scalability of the proposed method as well as an extension to more general cases.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

Energy consumption is one of the important issues in communication networks, and it is expected that network devices such as network interface cards will be turned off to decrease the energy consumption. Moreover, fast failure recovery is an important issue in large-scale communication networks to minimize the impact of failure on data transmission. In order to realize both low energy consumption and fast failure recovery, a method called LE-MRC (Low-Energy based Multiple Routing Configurations) has been proposed. However, LE-MRC can degrade network robustness because some links ports are turned off for reducing the energy consumption. Nevertheless, network robustness is also important for maintaining the performance of data transmission and the network functionality. In this paper, for realizing both low energy consumption and fast failure recovery while maintaining network robustness, we propose Robustness and Low-Energy based Multiple Routing Configurations (RLE-MRC). In RLE-MRC, some links are categorized into unnecessary links, and those links are turned off to lower the energy consumption. In particular, the number of excluded links is determined based on the network robustness. As a result, the energy consumption can be reduced so as not to degrade the network robustness significantly. Simulations are conducted on some network topologies to evaluate the performance of RLE-MRC. We also use ns-3 to evaluate how the performance of data transmission and network robustness are changed by using RLE-MRC. Numerical examples show that the low energy consumption and the fast failure recovery can be achieved while maintaining network robustness by using RLE-MRC.

Using linear programming (LP) decoding based on alternating direction method of multipliers (ADMM) for low-density parity-check (LDPC) codes shows lower complexity than the original LP decoding. However, the development of the ADMM-LP decoding algorithm could still be limited by the computational complexity of Euclidean projections onto parity check polytope. In this paper, we proposed a bisection method iterative algorithm (BMIA) for projection onto parity check polytope avoiding sorting operation and the complexity is linear. In addition, the convergence of the proposed algorithm is more than three times as fast as the existing algorithm, which can even be 10 times in the case of high input dimension.

When AgSnO2 contacts were operated to break an inductive DC load current of 14V-12A, 20V-7A or 20V-17A at a contact opening speed of 10mm/sec or slower, application of an external magnetic field resulted in reductions in break arc durations even without magnetic blowing. Simple estimation of Lorentz force to be applied onto arc column revealed that a certain minimum magnitude of Lorentz force seems to be required for initiating arc blowing. Certain relationships between the Lorentz force magnitude and the timing of metallic-to-gaseous phase transition were also found to exist.

Emerging solid state drives (SSDs) based on a next-generation memory technology have been recently released in market. In this work, we call them low-latency SSDs because the device latency of them is an order of magnitude lower than that of conventional NAND flash SSDs. Although low-latency SSDs can drastically reduce an I/O latency perceived by an application, the overhead of OS processing included in the I/O latency has become noticeable because of the very low device latency. Since the OS processing is executed on a CPU core, its operating frequency should be maximized for reducing the OS overhead. However, a higher core frequency causes the higher CPU power consumption during I/O accesses to low-latency SSDs. Therefore, we propose the device utilization-aware DVFS (DU-DVFS) technique that periodically monitors the utilization of a target block device and applies dynamic voltage and frequency scaling (DVFS) to CPU cores executing I/O-intensive processes only when the block device is fully utilized. In this case, DU-DVFS can reduce the CPU power consumption without hurting performance because the delay of OS processing incurred by decreasing the core frequency can be hidden. Our evaluation with 28 I/O-intensive workloads on a real server containing an Intel® Optane™ SSD demonstrates that DU-DVFS reduces the CPU power consumption by 41.4% on average (up to 53.8%) with a negligible performance degradation, compared to a standard DVFS governor on Linux. Moreover, the evaluation with multiprogrammed workloads composed of I/O-intensive and non-I/O-intensive programs shows that DU-DVFS is also effective for them because it can apply DVFS only to CPU cores executing I/O-intensive processes.

The fifth generation mobile communication system (5G) is designed to have new radio capabilities to support not only conventional enhanced Mobile Broadband (eMBB) communications but also new machine type communications such as Ultra-Reliable Low-Latency communications (URLLC) and massive Machine Type communications (m-MTC). In such new areas of URLLC and m-MTC, mobile operators need to explore new use cases and/or applications together with vertical industries, the industries which are potential users of 5G, in order to fully exploit the new 5G capabilities. Intelligent Transport System (ITS), including automated driving, is one of the most promising application areas of 5G since it requires both ultra-reliable and low-latency communications. We are actively working on the research and development of truck platooning as a new 5G application. We have developed a field trial system for vehicular-to-network (V2N) communications using 5G prototype equipment and actual large-size trucks in order to assess 5G capabilities, including ultra-low-latency, in automotive test courses in the field. This paper discusses the fundamental performance evaluation required for vehicular communications between platooning trucks, such as low-latency message communication for vehicle control and low-latency video monitoring of following platooning truck vehicles. The paper also addresses the field evaluation results of 5G V2N communications in a rural area. It clarifies the fundamental radio propagation issues at the leading and the following vehicles in truck platooning for V2N communications, and discusses the impact of the radio propagation over a road to the over-the-air transmission performance of 5G V2N communications.