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[Keyword] multiple-valued logic(61hit)

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  • An Algebraic Approach to Verifying Galois-Field Arithmetic Circuits with Multiple-Valued Characteristics

    Akira ITO  Rei UENO  Naofumi HOMMA  

     
    PAPER-Logic Design

      Pubricized:
    2021/04/28
      Vol:
    E104-D No:8
      Page(s):
    1083-1091

    This study presents a formal verification method for Galois-field (GF) arithmetic circuits with the characteristics of more than two values. The proposed method formally verifies the correctness of circuit functionality (i.e., the input-output relations given as GF-polynomials) by checking the equivalence between a specification and a gate-level netlist. We represent a netlist using simultaneous algebraic equations and solve them based on a novel polynomial reduction method that can be efficiently applied to arithmetic over extension fields $mathbb{F}_{p^m}$, where the characteristic p is larger than two. By using the reverse topological term order to derive the Gröbner basis, our method can complete the verification, even when a target circuit includes bugs. In addition, we introduce an extension of the Galois-Field binary moment diagrams to perform the polynomial reductions faster. Our experimental results show that the proposed method can efficiently verify practical $mathbb{F}_{p^m}$ arithmetic circuits, including those used in modern cryptography. Moreover, we demonstrate that the extended polynomial reduction technique can enable verification that is up to approximately five times faster than the original one.

  • Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers

    Rei UENO  Naofumi HOMMA  Takafumi AOKI  

     
    PAPER-VLSI Architecture

      Pubricized:
    2017/05/19
      Vol:
    E100-D No:8
      Page(s):
    1603-1610

    This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p≥3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(pm) multipliers for different p-values. In addition, we evaluate the performance of three types of GF(2m) multipliers and typical GF(pm) multipliers (p≥3) empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(pm) having extension degrees greater than 128.

  • Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

    Akira MOCHIZUKI  Hirokatsu SHIRAHAMA  Yuma WATANABE  Takahiro HANYU  

     
    PAPER-Communication for VLSI

      Vol:
    E97-D No:9
      Page(s):
    2304-2311

    An energy-efficient intra-chip communication link circuit with ternary current signaling is proposed for an asynchronous Network-on-Chip. The data signal encoded by an asynchronous three-state protocol is represented by a small-voltage-swing three-level intermediate signal, which results in the reduction of transition delay and achieving energy-efficient data transfer. The three-level voltage is generated by using a combination of dynamically controlled current sources with feedback loop mechanism. Moreover, the proposed circuit contains a power-saving scheme where the dynamically controlled transistors also are utilized. By cutting off the current paths when the data transfer on the communication link is inactive, the power dissipation can be greatly reduced. It is demonstrated that the average data-transfer speed is about 1.5 times faster than that of a binary CMOS implementation using a 130nm CMOS technology at the supply voltage of 1.2V.

  • Local Search with Probabilistic Modeling for Learning Multiple-Valued Logic Networks

    Shangce GAO  Qiping CAO  Masahiro ISHII  Zheng TANG  

     
    PAPER-Neural Networks and Bioengineering

      Vol:
    E94-A No:2
      Page(s):
    795-805

    This paper proposes a probabilistic modeling learning algorithm for the local search approach to the Multiple-Valued Logic (MVL) networks. The learning model (PMLS) has two phases: a local search (LS) phase, and a probabilistic modeling (PM) phase. The LS performs searches by updating the parameters of the MVL network. It is equivalent to a gradient decrease of the error measures, and leads to a local minimum of error that represents a good solution to the problem. Once the LS is trapped in local minima, the PM phase attempts to generate a new starting point for LS for further search. It is expected that the further search is guided to a promising area by the probability model. Thus, the proposed algorithm can escape from local minima and further search better results. We test the algorithm on many randomly generated MVL networks. Simulation results show that the proposed algorithm is better than the other improved local search learning methods, such as stochastic dynamic local search (SDLS) and chaotic dynamic local search (CDLS).

  • Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources

    Kwang-Jow GAN  Dong-Shong LIANG  Yan-Wun CHEN  

     
    PAPER-Multiple-Valued VLSI Technology

      Vol:
    E93-D No:8
      Page(s):
    2068-2072

    The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

  • Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor

    Naofumi HOMMA  Yuichi BABA  Atsushi MIYAMOTO  Takafumi AOKI  

     
    PAPER-Application of Multiple-Valued VLSI

      Vol:
    E93-D No:8
      Page(s):
    2117-2125

    This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.

  • Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits

    Motoi INABA  Koichi TANNO  Hiroki TAMURA  Okihiko ISHIZUKA  

     
    PAPER-Multiple-Valued VLSI Technology

      Vol:
    E93-D No:8
      Page(s):
    2073-2079

    In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

  • Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques

    Yasushi YUMINAKA  Yasunori TAKAHASHI  Kenichi HENMI  

     
    PAPER-Multiple-Valued VLSI Technology

      Vol:
    E93-D No:8
      Page(s):
    2109-2116

    This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

  • A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations

    Noboru TAKAGI  

     
    PAPER-Logic Design

      Vol:
    E93-D No:8
      Page(s):
    2040-2047

    Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

  • Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme

    Hirokatsu SHIRAHAMA  Takashi MATSUURA  Masanori NATSUI  Takahiro HANYU  

     
    PAPER-Multiple-Valued VLSI Technology

      Vol:
    E93-D No:8
      Page(s):
    2080-2088

    A multiple-valued current-mode (MVCM) circuit using current-flow control is proposed for a power-greedy sequential linear-array system. Whenever operation is completed in processing element (PE) at the present stage, every possible current source in the PE at the previous stage is cut off, which greatly reduces the wasted power dissipation due to steady current flows during standby states. The completion of the operation can be easily detected using "operation monitor" that observes input and output signals at latches, and that generates control signal immediately at the time completed. Since the wires of data and control signals are shared in the proposed MVCM circuit, no additional wires are required for current-flow control. In fact, it is demonstrated that the power consumption of the MVCM circuit using the proposed method is reduced to 53 percent in comparison with that without current-source control.

  • An Improved Local Search Learning Method for Multiple-Valued Logic Network Minimization with Bi-objectives

    Shangce GAO  Qiping CAO  Catherine VAIRAPPAN  Jianchen ZHANG  Zheng TANG  

     
    PAPER-Neural Networks and Bioengineering

      Vol:
    E92-A No:2
      Page(s):
    594-603

    This paper describes an improved local search method for synthesizing arbitrary Multiple-Valued Logic (MVL) function. In our approach, the MVL function is mapped from its algebraic presentation (sum-of-products form) on a multiple-layered network based on the functional completeness property. The output of the network is evaluated based on two metrics of correctness and optimality. A local search embedded with chaotic dynamics is utilized to train the network in order to minimize the MVL functions. With the characteristics of pseudo-randomness, ergodicity and irregularity, both the search sequence and solution neighbourhood generated by chaotic variables enables the system to avoid local minimum settling and improves the solution quality. Simulation results based on 2-variable 4-valued MVL functions and some other large instances also show that the improved local search learning algorithm outperforms the traditional methods in terms of the correctness and the average number of product terms required to realize a given MVL function.

  • Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation

    Masatomo MIURA  Takahiro HANYU  

     
    PAPER

      Vol:
    E91-C No:4
      Page(s):
    589-594

    In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90 nm CMOS technology is superior to those of the corresponding ordinary implementation.

  • A Stochastic Dynamic Local Search Method for Learning Multiple-Valued Logic Networks

    Qiping CAO  Shangce GAO  Jianchen ZHANG  Zheng TANG  Haruhiko KIMURA  

     
    PAPER-Neural Networks and Bioengineering

      Vol:
    E90-A No:5
      Page(s):
    1085-1092

    In this paper, we propose a stochastic dynamic local search (SDLS) method for Multiple-Valued Logic (MVL) learning by introducing stochastic dynamics into the traditional local search method. The proposed learning network maintains some trends of quick descent to either global minimum or a local minimum, and at the same time has some chance of escaping from local minima by permitting temporary error increases during learning. Thus the network may eventually reach the global minimum state or its best approximation with very high probability. Simulation results show that the proposed algorithm has the superior abilities to find the global minimum for the MVL network learning within reasonable number of iterations.

  • Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry

    Akira MOCHIZUKI  Hirokatsu SHIRAHAMA  Takahiro HANYU  

     
    PAPER-Digital

      Vol:
    E90-C No:4
      Page(s):
    683-691

    This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

  • Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic

    Naofumi HOMMA  Takafumi AOKI  Tatsuo HIGUCHI  

     
    PAPER

      Vol:
    E89-C No:11
      Page(s):
    1645-1654

    This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.

  • Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

    Akira MOCHIZUKI  Hirokatsu SHIRAHAMA  Takahiro HANYU  

     
    PAPER

      Vol:
    E89-C No:11
      Page(s):
    1591-1597

    A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

  • A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic

    Katsuhiko DEGAWA  Takafumi AOKI  Tatsuo HIGUCHI  Hiroshi INOKAWA  Yasuo TAKAHASHI  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1827-1836

    This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

  • Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic

    Md.Munirul HAQUE  Michitaka KAMEYAMA  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1869-1875

    A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

  • A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter

    Hiroshi INOKAWA  Yasuo TAKAHASHI  Katsuhiko DEGAWA  Takafumi AOKI  Tatsuo HIGUCHI  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1818-1826

    This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

  • Voltage-Mode Multiple-Valued Logic Adder Circuits

    Ioannis M. THOIDIS  Dimitrios SOUDRIS  Adonios THANAILAKIS  

     
    PAPER-Electronic Circuits

      Vol:
    E87-C No:6
      Page(s):
    1054-1061

    Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.

1-20hit(61hit)