This paper summarizes our recent studies on architecture, photonic integration, system validation and networking performance analysis of a flexible low-latency interconnect optical network switch (Flex-LIONS) for datacenter and high-performance computing (HPC) applications. Flex-LIONS leverages the all-to-all wavelength routing property in arrayed waveguide grating routers (AWGRs) combined with microring resonator (MRR)-based add/drop filtering and multi-wavelength spatial switching to enable topology and bandwidth reconfigurability to adapt the interconnection to different traffic profiles. By exploiting the multiple free spectral ranges of AWGRs, it is also possible to provide reconfiguration while maintaining minimum-diameter all-to-all interconnectivity. We report experimental results on the design, fabrication, and system testing of 8×8 silicon photonic (SiPh) Flex-LIONS chips demonstrating error-free all-to-all communication and reconfiguration exploiting different free spectral ranges (FSR0 and FSR1, respectively). After reconfiguration in FSR1, the bandwidth between the selected pair of nodes is increased from 50Gb/s to 125Gb/s while an all interconnectivity at 25Gb/s is maintained using FSR0. Finally, we investigate the use of Flex-LIONS in two different networking scenarios. First, networking simulations for a 256-node datacenter inter-rack communication scenario show the potential latency and energy benefits when using Flex-LIONS for optical reconfiguration based on different traffic profiles (a legacy fat-tree architecture is used for comparison). Second, we demonstrate the benefits of leveraging two FSRs in an 8-node 64-core computing system to provide reconfiguration for the hotspot nodes while maintaining minimum-diameter all-to-all interconnectivity.

We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications. To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation (PAM) 4 and wavelength-division-multiplexing technologies were also introduced to enhance the transmission capacity.

High-performance computing (HPC) has penetrated into various research fields, yet the increase in computing power is limited by conventional electrical interconnections. The proposed architecture, NEST, exploits wavelength routing in arrayed waveguide grating routers (AWGRs) to achieve a scalable, low-latency, and high-throughput network. For the intra pod and inter pod communication, the symmetrical topology of NEST reduces the network diameter, which leads to an increase in latency performance. Moreover, the proposed architecture enables exponential growth of network size. Simulation results demonstrate that NEST shows 36% latency improvement and 30% throughput improvement over the dragonfly on an average.

Optical interconnect is a promising candidate for network on chip. As the key element in the network on chip, the routers greatly affect the performance of the whole system. In this letter, we proposed a new router architecture, Waffle, based on compact 2×2 hybrid photonic-plasmonic switching elements. Also, an optimized architecture, Waffle-XY, was designed for the network employed XY routing algorithm. Both Waffle and Waffle-XY are strictly non-blocking architectures and can be employed in the popular mesh-like networks. Theoretical analysis illustrated that Waffle and Waffle-XY possessed a better performance compared with several representative routers.

To realize three-dimensional (3D) optical interconnection on large-scale integration (LSI) circuits, layer-to-layer couplers based on Si-photonics platform were reviewed. In terms of optical cross talk, more than 1 µm layer distance is required for 3D interconnection. To meet this requirement for the layer-to-layer optical coupler, we proposed two types of couplers: a pair of grating couplers with metal mirrors for multi-layer distance coupling and taper-type directional couplers for neighboring layer distance coupling. Both structures produced a high coupling efficiency with relatively compact (∼100 µm) device sizes with a complementary metal oxide semiconductor (CMOS) compatible fabrication process.

Ring-based topology is popular for optical network-on-chip. However, the network congestion is serious for ring topology, especially when optical circuit-switching is employed. In this paper, we proposed an algorithm to build a low congestion multi-ring architecture for optical network-on-chip without additional wavelength or scheduling overhead. A network congestion model is established with new network congestion factor defined. An algorithm is developed to optimize the low congestion multi-ring topology. Finally, a case study is shown and the simulation results by OPNET verify the superiority over the traditional ONoC architecture.

This paper describes the design and experiment results of a 25Gbps vertical-cavity surface emitting laser (VCSEL) driver circuit for a multi channel optical transmitter. To compensate for the non-linearity of the VCSEL and achieve high speed data rate communication, an asymmetric pre-emphasis technique is proposed for the VCSEL driver. An asymmetric pre-emphasis signal can be created by adjusting the duty ratio of the emphasis signal. The VCSEL driver adopts a double cascode connection that can apply a drive current from a high voltage DC bias and feed-forward compensation that can enhance the band-width for common-cathode VCSEL. For the design of the optical module structure, a two-tier low temperature co-fired ceramics (LTCC) package is adopted to minimize the wire bonding between the signal pad on the LTCC and the anode pad on the VCSEL. This structure and circuit reduces the simulated deterministic jitter from 12.7 to 4.1ps. A test chip was fabricated with the 65-nm standard CMOS process and demonstrated to work as an optical transmitter. An experimental evaluation showed that this VCSEL driver with asymmetric pre-emphasis reduced the total deterministic jitter up to 8.6ps and improved the vertical eye opening ratio by 3% compared with symmetric pre-emphasis at 25Gbps with a PRBS=29-1 test signal. The power consumption of the VCSEL driver was 3.0mW/Gbps/ch at 25Gbps. An optical transmitter including the VCSEL driver achieved 25-Gbps, 4-ch fully optical links.

An ultra-compact InGaAs photodetector (PD) is demonstrated based on a photonic crystal (PhC) waveguide to meet the demand for a photoreceiver for future dense photonic integration. Although the PhC-PD has a length of only 1.7µm and a capacitance of less than 1fF, a high responsivity of 1A/W was observed both theoretically and experimentally. This low capacitance PD allows us to expect a resistor-loaded receiver to be realized that requires no electrical amplifiers. We fabricated a resistor-loaded PhC-PD for light-to-voltage conversion, and demonstrated a kV/W efficiency with a GHz bandwidth without using amplifiers. This will lead to a photoreceiver with an ultralow energy consumption of less than 1fJ/bit, which is a step along the road to achieving a dense photonic network and processor on a chip.

Silicon-on-insulator (SOI) has become one of the most famous materials in recent years, especially in silicon photonics applications. This paper presents a comparative performance of a SOI-based optical interconnect (OI) vs. an electrical interconnect (EI) for high-speed performances at a circuit level. The SOI-based optical waveguide was designed using OptiBPM to obtain a single mode condition (SMC). Then, the optical interconnect (OI) link was simulated in OptiSPICE and was tested as an interconnection in two-stage CS amplifiers. The results showed that the two-stage CS amplifier using OI offered several advantages in terms of electrical performances, such as voltage gain, frequency bandwidth, slew rate, and propagation delay, which makes it superior to the EI.

Triggered by the Great East Japan Earthquake in March 2011, the authors have been studying a resilient network whose key element is a movable and deployable ICT resource unit. The resilient network needs a function of robust and immediate connection to a wide area network active outside the damaged area. This paper proposes an application of digital coherent technology for establishing optical interconnection between the movable ICT resource unit and existing network nodes through a photonic network, rapidly, easily and with the minimum in manual work. We develop a prototype of a 100Gbit/s digital coherent transponder which is installable to our movable and deployable ICT resource unit and experimentally confirm the robust and immediate connection by virtue of the plug and play function.

This paper covers new architectures, technologies, and performance benchmarking together with prospects for high productivity and high performance computing enabled by photonics. The exponential and sustained increases in computing and data center needs are driving the demands for exascale computing in the future. Power-efficient and parallel computing with balanced system design is essential for reaching that goal as should support ∼billion total concurrencies and ∼billion core interconnections with ∼exabyte/second bisection bandwidth. Photonic interconnects offer a disruptive technology solution that fundamentally changes the computing architectural design considerations. Optics provide ultra-high throughput, massive parallelism, minimal access latencies, and low power dissipation that remains independent of capacity and distance. In addition to the energy efficiency and many of the fundamental physical problems, optics will bring high productivity computing where programmers can ignore locality between billions of processors and memory where data resides. Repeaterless interconnection links across the entire computing system and all-to-all massively parallel interconnection switch will significantly transform not only the hardware aspects of computing but the way people program and harness the computing capability. This impacts programmability and productivity of computing. Benchmarking and optimization of the configuration of the computing system is very important. Practical and scalable deployment of photonic interconnected computing systems are likely to be aided by emergence of athermal silicon photonics and hybrid integration technologies.

A new wavelength-selective optical modulator was proposed and discussed. The modulator consists of three kinds of distributed Bragg reflectors (DBRs) integrated in a single straight waveguide. The waveguide can guide TE$_0$ and TE$_1$ modes, and an in-line Michelson interferometer is constructed by the three DBRs. An operation-wavelength wave among incident wavelength-division-multiplexed TE$_1$ guided waves is split into TE$_0$ and TE$_1$ guided waves by one of DBRs, and combined by the same DBR to be TE$_0$ output wave with interference after one of waves is phase-modulated. A modulator using an electro-optic (EO) polymer is designed, and the static performance was predicted theoretically. An operation principle was confirmed experimentally by a prototype device utilizing a thermo-optic effect instead of the EO effect.

Silicon photonics Network-on-Chips (NoCs) have emerged as an attractive solution to alleviate the high power consumption of traditional electronic interconnects. In this paper, we propose a fully optical ring NoC that combines static and dynamic wavelength allocation communication mechanisms. A different wavelength-channel is statically allocated to each destination node for light weight communication. Contention of simultaneous communication requests from multiple source nodes to the destination is solved by a token based arbitration for the particular wavelength-channel. For heavy load communication, a multiwavelength-channel is available by requesting it in execution time from source node to a special node that manages dynamic allocation of the shared multiwavelength-channel among all nodes. We combine these static and dynamic communication mechanisms in a same network that introduces selection techniques based on message size and congestion information. Using a photonic NoC simulator based on Phoenixsim, we evaluate our architecture under uniform random, neighbor, and hotspot traffic patterns. Simulation results show that our proposed fully optical ring NoC presents a good performance by utilizing adequate static and dynamic channels based on the selection techniques. We also show that our architecture can reduce by more than half, the energy consumption necessary for arbitration compared to hybrid photonic ring and mesh NoCs. A comparison with several previous works in term of architecture hardware cost shows that our architecture can be an attractive cost-performance efficient interconnection infrastructure for future SoCs and CMPs.

One of the most serious challenges facing the exponential performance growth in the information industry is a bandwidth bottleneck in inter-chip interconnects. We therefore propose a photonics-electronics convergence system with a silicon optical interposer. We examined integration between photonics and electronics and integration between light sources and silicon substrates, and we fabricated a conceptual model of the proposed system based on the results of those examinations. We also investigated the configurations and characteristics of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical splitters, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high-density optical interposer by using silicon photonics integrated with these optical components on a single silicon substrate. As a result, we achieved error-free data transmission at 12.5 Gbps and a high bandwidth density of 6.6 Tbps/cm2 with the optical interposer. We think that this technology will solve the bandwidth bottleneck problem.

We describe 25-Gb/s error-free transmission over multi-mode fiber (MMF) by using a transmitter based on a 1.3-µm lens-integrated surface-emitting laser (LISEL) and a CMOS laser-diode driver (LDD). It demonstrates 25-Gb/s error-free transmission over 30-m MMF under the overfilled-launch condition and over 150-m MMF with a power penalty less than 1.0 dB under the underfilled-launch condition.

To meet the demand for light sources for on-chip optical interconnections, we demonstrate the continuous-wave (CW) operation of photonic-crystal (PhC) nanocavity lasers at up to 89.8 by using InP buried heterostructures (BH). The wavelength of a PhC laser can be precisely designed over a wide range exceeding 100 nm by controlling the lattice constant of the PhC. The dynamic responses of the PhC laser are also demonstrated with a 3-dB bandwidth of over 7.0 GHz at 66.2. These results reveal the laser's availability for application to wavelength division multiplexed (WDM) optical interconnection on CMOS chips. We discuss the total bandwidths of future on-chip optical interconnections, and report the capabilities of PhC lasers.

We demonstrate the wavelength trimming of MEMS VCSELs by etching a cantilever-shaped top mirror using FIB etching. The proposed technique can be used for the post-process precise wavelength allocation of athermal MEMS VCSELs. The modeling and experimental results on 850 nm MEMS VCSELs are presented. The results show a possibility of realizing both red-shift and blue-shift wavelength changes by choosing the etching area of the cantilever.

We have developed InGaAs-based VCSELs operating around 1.1 µm for high-speed optical interconnections. By applying GaAsP barrier layers, temperature characteristics were considerably improved compared to GaAs barrier layers. As a result, 25 Gbps 100 error-free operation was achieved. These devices also exhibited high reliability. No degradation was observed over 3,000 hours under operation temperature of 150 and current density of 19 kA/cm2. We also developed VCSELs with tunnel junctions for higher speed operation. High modulation bandwidth of 24 GHz and a relaxation oscillation frequency of 27 GHz were achieved. 40 Gbps error-free operation was also demonstrated.

We propose a gap-less optical interconnection between BGA package and board for practical on-board, chip-to-chip optical interconnection. The optical interconnect consists of polymer optical waveguides, an integral mirror on the PWB (printed wiring board), an optical via hole through package, and a connection structure and method requiring no alignment process. Optical waveguide, mirror, waveguide extensions and alignment studs were fabricated on the PWB as horizontal optical interconnect. Coaxial structured optical vias with core and cladding were formed through the package and with precise holes for alignment. Two packages were attached onto the PWB using standard BGA technology utilizing passive optical alignment. The optical characteristics and 10 Gbit/s open-eye diagram were measured. A completely gap-less three dimensional optical interconnect between package-PWB-package was demonstrated.

LSI on-chip optical interconnections are discussed from the viewpoint of a comparison between optical and electrical interconnections. Based on a practical prediction of our optical device development, optical interconnects will have an advantage over electrical interconnects within a chip that has an interconnect length less than about 10 mm at the hp32-22 nm technology node. Fundamental optical devices and components used in interconnections have also been introduced that are small enough to be placed on top of a Si LSI and that can be fabricated using methods compatible with CMOS processes. A SiON waveguide showed a low propagation loss around 0.3 dB/cm at a wavelength of 850 nm, and excellent branching characteristics were achieved for MMI (multimode interference) branch structures. A Si nano-photodiode showed highly enhanced speed and efficiency with a surface plasmon antenna. By combining our Si nano-photonic devices with the advanced TIA-less optical clock distribution circuits, clock distribution above 10 GHz can be achieved with a small footprint on an LSI chip.