Since sentences are the basic propositional units of text, knowing their themes should help in completing various tasks such as automatic summarization requiring the knowledge about the semantic content of text. Despite the importance of determining the theme of a sentence, however, few studies have investigated the problem of automatically assigning a theme to a sentence. In this paper, we examine the notion of sentence theme and propose an automatic scheme where head-driven patterns are used for theme assignment. We tested our scheme with sentences in encyclopedia articles and obtained a promising result of 98.96% in F-score for training data and 88.57% for testing data, which outperform the baseline using all but the head-driven patterns.

Recently, the radix-3 representation of integers is used for the efficient implementation of pairing based cryptosystems. In this paper, we propose non-adjacent form of radix-r representation (rNAF) and efficient algorithms for generating rNAF. The number of non-trivial digits is (r-2)(r+1)/2 and its average density of non-zero digit is asymptotically (r-1)/(2r-1). For r=3, the non-trivial digits are {2, 4} and the non-zero density is 0.4. We then investigate the width-w version of rNAF for the general radix-r representation, which is a natural extension of the width-w NAF. Finally we compare the proposed algorithms with the generalized NAF (gNAF) discussed by Joye and Yen. The proposed scheme requires a larger table but its non-zero density is smaller even for large radix. We explain that gNAF is a simple degeneration of rNAF--we can consider that rNAF is a canonical form for the radix-r representation. Therefore, rNAF is a good alternative to gNAF.

This paper introduces the concept of "revocable unlinkability" for unlinkable anonymous signatures and proposes a generalized scheme that modifies the signatures to include revocable unlinkability. Revocable unlinkability provides a condition in which multiple messages signed using an unlinkable anonymous signature are unlinkable for anyone except the unlinkability revocation manager. Noteworthy is that the identifier of the signer is kept secret from the manager. In addition, examples are presented in which the proposed scheme is applied to existing group/ring signatures. The proposed scheme employs a verifiable MIX-net to shuffle the identifiers of all potential signers, thus giving it the potential for wide application to unlinkable anonymous signatures.

Contract signing is a practical application of the fair exchange of digital signatures. This application used to be realized by directly adopting the results of the fair exchange of signatures, which do not completely meet the requirements of the signing of a secret contract. The assistance of a trusted third party (TTP) and some cryptographic technology are required to allow two parties to exchange their signatures through the network in a fair manner because these two parties potentially may be dishonest or mistrust each other. This paper presents a subtle method of preventing the off-line TTP from gaining the exchanged signature and the corresponding message when a dispute occurs between the two parties wherein the TTP is required to take part in the exchange procedure. An advanced concept, the non-disclosure property, is proposed in order to prevent a party from misusing evidence left during the exchange process. Two approaches, namely the secret divide method and the convertible signature are demonstrated. To satisfy the properties of the traditional paper-based contract signing, the technique of multi-signature scheme is used in the proposed protocols.

This paper investigates some modular powering functions suitable for cryptography. It is well known that the Rabin encryption function is a 4-to-1 mapping and breaking its one-wayness is secure under the factoring assumption. The previously reported encryption schemes using a powering function are variants of either the 4-to-1 mapping or higher n-to-1 mapping, where n > 4. In this paper, we propose an optimized powering function that is a 3-to-1 mapping using a p2q-type modulus. The one-wayness of the proposed powering function is as hard as the infeasibility of the factoring problem. We present an efficient algorithm for computing the decryption for a p2q-type modulus, which requires neither modular inversion nor division. Moreover, we construct new provably secure digital signatures as an application of the optimized functions. In order to achieve provable security in the random oracle model, we usually randomize a message using random hashing or padding. However, we have to compute the randomization again if the randomized message is a non-cubic residue element--it is inefficient for long messages. We propose an algorithm that can deterministically find the unique cubic residue element for a randomly chosen element.

In this paper, we present previously unproposed schemes for encryption with anonymity and ring signature by applying two techniques. That is, we construct a key-privacy encryption scheme by using N-ary representation, and a ring signature scheme by using the repetition of evaluation of functions. We analyze precisely the properties of these schemes and show their advantage and disadvantage.

In this paper, we analyse the Libert-Quisquater's q-DH signcryption scheme proposed in SCN'2004. Although the paper proved that their scheme is secure against adaptive chosen ciphertext attacks in the random oracle model, we disprove their claim and show that their scheme is not even secure against non-adaptive chosen ciphtertext attacks, which is the weaker security than the adaptive chosen ciphertext attacks. We further show that the semantically secure symmetric encryption scheme defined in their paper is not sufficient to guarantee their signcryption scheme to be secure against adaptive chosen ciphertext attacks.

This paper presents a multi-matcher on-line signature verification system which fuses the verification scores in pen-position parameter and pen-movement angle one at total decision. Features of pen-position and pen-movement angle are extracted by the sub-band decomposition using the Discrete Wavelet Transform (DWT). In the pen-position, high frequency sub-band signals are considered as individual features to enhance the difference between a genuine signature and its forgery. On the other hand, low frequency sub-band signals are utilized as features for suppressing the intra-class variation in the pen-movement angle. Verification is achieved by the adaptive signal processing using the extracted features. Verification scores in the pen-position and the pen-movement angle are integrated by using a weighted sum rule to make total decision. Experimental results show that the fusion of pen-position and pen-movement angle can improve verification performance.

Digital watermarking used for fingerprinting may receive a collusion attack; two or more users collude, compare their data, find a part of embedded watermarks, and make an unauthorized copy by masking their identities. In this paper, assuming that at most c users collude, we give a characterization of the fingerprinting codes that have the best security index in a sense of "(c,p/q)-secureness" proposed by Orihara et al. The characterization is expressed in terms of intersecting families of sets. Using a block design, we also show that a distributor of data can only find asymptotically a set of c users including at least one culprit, no matter how good fingerprinting code is used.

The Reed-Solomon code is a versatile channel code pervasively used for communication and storage systems. The bit-serial Reed-Solomon encoder has a simple structure, although it is somewhat difficult to understand the algorithm without considerable theoretical background. Some professionals and students, not able to understand the algorithm thoroughly, might need to implement the bit-serial encoder for themselves. In this letter, a step-by-step method is presented for the implementation of the bit-serial encoder even without understanding the internal algorithm, which would be helpful for VHDL, DSP, and simulation programming.

This paper tackles the problem of detecting a random signal embedded in additive white noise. Although the likelihood ratio test (LRT) is the well-known optimum detector for this problem, it may not be easily realized in applications such as radar, sonar, seismic, digital communications, speech analysis and automatic fault detection in machinery, for which suboptimal quadratic detectors have been extensively employed. In this paper, the relationships between four suboptimal quadratic detection schemes, namely, the energy, matched subspace, maximum deflection ratio as well as spectrum matching detectors, and the LRT are studied. In particular, we show that each of those suboptimal detectors can approach the optimal LRT under certain operating conditions. These results are verified via Monte Carlo simulations.

In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

In this Letter, linear least squares (LLS) techniques for phase estimation of real sinusoidal signals with known or unknown amplitudes are studied. It is proved that the asymptotic performance of the LLS approach attains Cramér-Rao lower bound. For the case of a single tone, a novel LLS algorithm with unit-norm constraint is derived. Simulation results are also included for algorithm evaluation.

Designing a software architecture that satisfies multiple quality requirements is a difficult undertaking. This is mainly due to the fact that architects must be able to explore a broad range of architectural choices and analyze tradeoffs among them in light of multiple quality requirements. As the size and complexity of the system increase, architectural design space to be explored and analyzed becomes more complex. In order to systematically manage the complexity, this paper proposes a method that guides architects to explore and analyze architectural decisions in a top-down manner. In the method, architectural decisions that have global impacts on given quality requirements are first explored and analyzed and those that have local impacts are then taken into account in the context of the decisions made in the previous step. This approach can cope with the complexity of large-scale architectural design systematically, as architectural decisions are analyzed and made following the abstraction hierarchy of quality requirements. To illustrate the concepts and applicability of the proposed method, we have applied this method to the architectural design of the computer used for the continuous casting process by an iron and steel manufacturer.

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

Signal detectors generally utilize nonlinear statistics of an original observation rather than the original observation as it is. The sign statistic, a typical example of the nonlinear statistics, is the sign information of an observation and the sign detector relies only on the sign statistic. Since either detector might be of a better performance depending on the situation, it is quite important to determine which is the best performer among the detectors, based on the given situational information about noise and signal strength. In this letter, a qualitative analysis is presented that the correlation coefficients between the statistics and original observation can be used to predict the asymptotic performance of a detector utilizing one of the statistics, relative to the other detectors.

This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

An efficient pad assignment methodology to minimize voltage drop on a power distribution network is proposed. A combination of successive pad assignment (SPA) with incremental matrix inversion (IMI) determines both location and number of power supply pads to satisfy drop voltage constraint. The SPA creates an equivalent resistance matrix which preserves both pad candidates and power consumption points as external ports so that topological modification due to connection or disconnection between voltage sources and candidate pads is consistently represented. By reusing sub-matrices of the equivalent matrix, the SPA greedily searches the next pad location that minimizes the worst drop voltage. Each time a candidate pad is added, the IMI reduces computational complexity significantly. Experimental results including a 400 pad problem show that the proposed procedures efficiently enumerate pad order in a practical time.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.