We have launched "Highly-Reliable Embedded Software Development" Project, held as a part of e-Society Project, supported by Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. The aim of this project is to enable the industry to produce highly reliable and advanced software by introducing latest software technologies into embedded software development. In this paper, we introduce the overview of the projects and our activities and results so far.

Mainly, a uniform linear array (ULA) has been used for DOA estimation of coherent signals because we can apply the spatial smoothing preprocessing (SSP) technique. However, estimation by a ULA has ambiguity due to the symmetry, and the estimation accuracy depends on the DOA. Although these problems can be solved by using a uniform circular array (UCA), we cannot estimate the DOA of coherent signals because the SSP technique cannot be applied directly to the UCA. In this paper, we propose to estimate 2-dimensional DOA (polar angles and azimuth angles) estimation of coherent signals using a cylindrical array which is composed of stacked UCAs.

The wavelength-division multiplexing (WDM) technology has been popular in communication societies for providing very large communication bands by multiple lightpaths with different wavelengths on a single optical fiber. Particularly, a double-ring optical network architecture based on the packet-over-WDM technology such as the HORNET architecture, has been extensively studied as a next generation platform for metropolitan area networks (MANs). Each node in this architecture is equipped with a wavelength-fixed optical-drop and a fast tunable transmitter so that a lightpath can be established between any pair of nodes without wavelength conversions. In this paper, we formulate the optical-drop wavelength assignment problem (ODWAP) for efficient wavelength reuse under heterogeneous traffic in this network, and prove the NP-completeness of its decision problem. Then, we propose a simple heuristic algorithm for the basic case of ODWAP. Through extensive simulations, we demonstrate the effectiveness of our approach in reducing waiting times for packet transmissions when a small number of wavelengths are available to retain the network cost for MANs.

An essential issue in designing, operating and managing a modern network is to assure end-to-end QoS from users perspective, and in the meantime to optimize a certain average performance objective from the systems perspective. So in the first part of this paper, we address the above issue by using the rerouting approach, where the objective is to minimize the average cross-network packet delay in virtual circuit networks with the consideration of an end-to-end delay constraint (DCR) for each O-D pair. The problem is formulated as a multicommodity network flow problem with integer routing decision variables, where additional end-to-end delay constraints are considered. As the traffic demands increases over time, the rerouting approach may not be applicable, which results in the necessity of capacity augmentation. Henceforth, the second part of this paper is to jointly consider the link capacity assignment and the routing problem (JCR) at the same time where the objective is to minimize the total link installation cost with considering the average and end-to-end delay constraints. Unlike previous research tackling this problem with a two-phase approach, we propose an integrated approach to considering the routing and capacity assignment at the same time. The difficulties of DCR and JCR result from the integrality nature and particularly the nonconvexity property associated with the end-to-end delay constraints. We propose novel Lagrangean relaxation based algorithms to solve the DCR and the JCR problems. Through computational experiments, we show that the proposed algorithms calculate near-optimal solutions for the DCR problem and outperform previous two-phase approach for the JCR problem under all tested cases.

In the next-generation networks, ultra high-speed data transmission will become necessary to support a variety of advanced point-to-point and multipoint multimedia services with stringent quality-of-service (QoS) constraints. Such a requirement desires the realization of optical WDM networks. Researches on multicast in optical WDM networks have become active for the purpose of efficient use of wavelength resources. Since multiple channels are more likely to share the same links in WDM multicast, effective routing and wavelength assignment (RWA) technology becomes very important. The introduction of the wavelength conversion technology leads to more efficient use of wavelength resources. This technology, however, has problems to be solved, and the number of wavelength converters will be restricted in the network. In this paper, we propose an effective WDM multicast design method on condition that wavelength converters on each switching node are restricted, which consists of three separate steps: routing, wavelength converter allocation, and wavelength assignment. In our proposal, preferentially available waveband is classified according to the scale of multicast group. Assuming that the number of wavelength converters on each switching node is limited, we evaluate its performance from a viewpoint of the call blocking probability.

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

This paper proposes a group signature scheme with efficient membership revocation. Though group signature schemes with efficient membership revocation based on a dynamic accumulator were proposed, the previous schemes force a member to change his secret key whenever he makes a signature. Furthermore, for the modification, the member has to obtain a public membership information of O(nN) bits, where n is the length of the RSA modulus and N is the total number of joining members and removed members. In our scheme, the signer needs no modification of his secret, and the public membership information has only K bits, where K is the maximal number of members. Then, for middle-scale groups with the size that is comparable to the RSA modulus size (e.g., up to about 1000 members for 1024 bit RSA modulus), the public membership information is a single small value only, while the signing/verification also remains efficient.

Fundamentals of parametric processing in highly nonlinear optical fiber are reviewed. Experimental procedures necessary for construction of one- and two-pump parametric amplifier architectures are described. Pump phase broadening, dispersion fluctuation and birefringence form basic impairment mechanisms in fiber parametric devices and are analyzed in two-pump parametric devices. Parametric signal processing is introduced with specific applications in all-optical regeneration, band conjugation, multicasting, packet switching and signal distortion reversal.

In this paper, we propose a global routing method for 2-layer BGA packages. In our routing model, the global routing for each net is uniquely determined by a via assignment of each net. Our global routing method starts from an initial monotonic via assignment and incrementally improves the via assignment to optimize the total wire length and the wire congestion. Experimental results show that our proposed method generates a better global routing efficiently.

Up to present, proposed are many multi-signature schemes in which signers use respective moduli in the signature generation process. The FDH-based schemes are proposed by Mitomi et al. and Lysyanskaya et al.. The PSS-based schemes are proposed by Kawauchi et al. and Komano et al.. The FDH-based schemes have the advantage that the signature size is independent of the number of the signers. However, since the signature generation algorithm is deterministic, it has a bad reduction rate as a defect. Consequently, the signers must unfortunately use the keys large enough to keep the security. On the other hand, in the PSS-based schemes, good reduction rates can be obtained since the signature generation algorithms are probabilistic. However, the size of the random component shall overflow the security parameter, and thereby the signature size shall grow by the total size of the random components used the signers. That means, if the size of the random component is smaller, the growth of the signature size can be kept smaller. In this paper, we propose new probabilistic multi-signature scheme, which can be proven secure despite that smaller random components are used. We compare the proposed scheme and two existing schemes. Finally, we conclude that the proposed scheme is so-called optimal due to.

Recently, various types of traffic have increased on the Internet with the development of broadband networks. However, it is difficult to guarantee QoS for each traffic type in current network environments. Moreover, it has been reported that bandwidth can be allocated to flows unfairly, and this can be an important issue for QoS guarantees. Therefore, we have proposed a flow-based queue management scheme, called Dual Metrics Fair Queueing (DMFQ), to improve the fairness and QoS per flow. DMFQ discards arrival packets by considering not only the arrival rate per flow but also the flow succession time. In addition, we have confirmed the effectiveness of DMFQ through several computer simulations. In this paper, we implement DMFQ with hardware for high-speed operation. Concretely, we propose the design policies and show the hardware design results.

In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

Penumbral imaging is a technique which exploits the fact that spatial information can be recovered from the shadow or penumbra that an unknown source casts through a simple large circular aperture. Since the technique is based on linear deconvolution, it is sensitive to noise. In this paper, a two-step method is proposed for decoding penumbral images: first, a noise-reduction algorithm based on ICA-domain (independent component analysis-domain) shrinkage is applied to smooth the given noise; second, the conventional linear deconvolution follows. The simulation results show that the reconstructed image is dramatically improved in comparison to that without the noise-removing filters, and the proposed method is successfully applied to real experimental X-ray imaging.

In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no-addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.

A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not probabilistic. Experiments on the ISCAS benchmark circuits show that the average diagnosis resolution is less than ten scan cells.

Several regular topologies have been proposed to be used as the logical topology for WDM networks. These topologies are usually evaluated and compared based on the metrics related to network performance. It can be simply shown that this is generally not sufficient since better network performance can be achieved by increasing more network facilities. However, doing this eventually increases the network cost. Thus, the comparison of topologies must be performed by using an evaluation function that includes both the network performance metric and the network cost. In this paper, we propose a model to find the optimum regular logical topology for wavelength routed WDM networks. ShuffleNet, de Bruijn graph, hypercube, Manhattan Street Network, and GEMNet are the five well-known and commonly used regular topologies compared in this paper. By solving the two subproblems on node placement optimization, and routing and wavelength assignment, we obtain the evaluation function used in the topology comparison. Numerical results show that GEMNet is the optimum logical topology for the wavelength routed WDM networks, where it can take one of the three forms of ShuffleNet, de Bruijn graph, and its own configurations.

In this paper, we analyse the signcryption scheme proposed by Libert and Quisquater in 2004 and show that their scheme does not meet the requirements as claimed in their paper in PKC'2004, such as, semantically secure against adaptive chosen ciphtertext attack, ciphertext anonymity and key invisibility.