Various trajectories of design, arising from the new methodology of analog network design, are analyzed. Several major criteria suggested for optimal selection of initial approximation to the design process permit the minimization of computer time. The initial approximation point is selected with regard to the previously revealed effect of acceleration of the design process. The concept of separatrix is defined making it possible to determine the optimal position of the initial approximation. The numerical results obtained for passive and active networks prove the possibility of optimal choice of the initial point in design process.

An explicit expression for the impulse response coefficients of the predictive FIR digital filters is derived. The formula specifies a four-parameter family of smoothing FIR digital filters containing the Savitsky-Goaly filters, the Heinonen-Neuvo polynomial predictors, and the smoothing differentiators of arbitrary integer orders. The Hahn polynomials, which are orthogonal with respect to a discrete variable, are the main tool employed in the derivation of the formula. A recursive formula for the computation of the transfer function of the filters, which is the z-transform of a terminated sequence of polynomial ordinates, is also introduced. The formula can be used to design structures with low computational complexity for filters of any order.

The ESIGN signature scheme was initially proposed in 1985. Since then, several variants have been proposed, but only a few have been formally supported using the methodology of provable security. In addition, these schemes are different from the ESIGN-PSS signature scheme submitted to ISO/IEC-14888-2 for standardization. It is believed that ESIGN-PSS is secure against the chosen-message attack, however, there has not yet been any report verifying this belief. This paper presents the security proofs of ESIGN-PSS and a variant of this scheme, denoted ESIGN-PSS-R, which is a signature scheme comprising the ESIGN signature mechanism and the PSS-R mechanism.

We developed a comprehensive simulation system for evaluating satellite-based navigation services in highly built-up areas; the system can accommodate Global Positioning System (GPS) multipath effects, as well as line-of-sight (LOS) and dilution of position (DOP) issues. For a more realistic simulation covering multipath and diffracted signal propagations, a 3D-ray tracing method was combined with a satellite orbit model and three-dimensional (3D) geographic information system (GIS) model. An accuracy estimation model based on a 3D position determination algorithm with a theoretical delay-locked loop (DLL) correlation computation could measure the extent to which multipath mitigation improved positioning accuracy in highly built-up areas. This system could even capture the multipath effect from an invisible satellite, one of the greatest factors in accuracy deterioration in highly built-up areas. Further, the simulation results of satellite visibility, DOP, and multipath occurrence were mapped to show the spatial distribution of GPS availability. By using object-oriented programming, our simulation system can be extended to other global navigation satellite systems (GNSSs) simply by adding the orbital information of the corresponding GNSS satellites. We demonstrated the applicability of our simulation system in an experimental simulation for Shinjuku, an area of Tokyo filled with skyscrapers.

For the optimization design of air circuit breaker (ACB), it is important and necessary to calculate the electro-dynamic repulsion force acting on the movable contact. A method based on 3-D FEM with the equations that describe the relationships among current, magnetic field and repulsion force, which takes the ferromagnet into account, is adopted to calculate the electro-dynamic repulsion force. The method enables one to analyze the factors that affect the electro-dynamic repulsion force, including the number of the movable conductor parallel branches as well as the location of the axis and the shape of the flexible connection. The discussion of the calculation results is also presented in this paper.

The large PAPR of orthogonal frequency division multiplexing (OFDM) transmission is one of the serious problems for mobile communications that require severe power saving. Iterative clipping and filtering is an effective method for the PAPR reduction of OFDM signals. This paper evaluates PAPR reduction effect with a graded band-limiting filter in the iterative clipping and filtering method. The evaluation result by computer simulation shows that the excellent peak reduction effect can be obtained in the fewer iteration numbers by using a roll-off filter instead of the conventional rectangular filter, and the iteration number with the roll-off filter achieving the same PAPR is fewer by twice. The result confirms that the clipping and filtering method by using a graded band-limiting filter can achieve low peak OFDM transmission with less computational complexity.

Recent theoretical and experimental studies indicate that spatial multiplexing (SM) systems have enormous potential for increasing the capacity of corresponding multiple input multiple output (MIMO) channels in rich scattering environments. In this paper, we propose a new recursion based algorithm for Bell Labs layered space time (BLAST) signal detection in SM systems. The new algorithm uses an inflated recursion in the initialization and a deflated recursion in the iteration stage: as a result, the complexity is greatly reduced and the irregularity issues are completely avoided. Compared with the conventional fastest recursive approach, the complexity of our proposal is lower by a factor of 2 and it is also very implementation friendly.

As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.

This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.

Wireless mesh networks (WMNs) are gaining significant momentum as a promising technology for the next-coming state-of-the-art wireless networking. Among many factors, the performance of WMNs would be largely affected by the properness of the deployed routing protocols and the efficient usage of wireless resources. Routing protocols are required to well capture WMNs' features while wireless channels should be used efficiently in order to accommodate high amount of traffics over the mesh backbone. Recently, a Tree-based Routing (TBR) protocol become a popular state-of-the-art proactive routing protocol and its tree-based broadcasting become an often used technique. Though TBR protocol is well-suited for WMNs' architecture and the skewed nature of traffic toward the root, the protocol in its current form faces issues which has to be addressed. Specifically, when some or all nodes are equipped with multiple radios, to reduce collision and co-channel interference, not only the parent-child relationship but also the sibling relationship need to be constructed by the TBR protocol in the multi-channel WMNs. In this paper, we propose a hybrid tree-based protocol for concurrent routing and channel assignment over WMNs. The protocol makes use of sibling links to mitigate the aforementioned shortcomings of TBR protocol. Moreover, in order to address high backbone traffic, the protocol integrates a receiver-based channel assignment scheme. The protocol efficiently deploys the parent-child topological relationships of nodes to enhance efficiency of broadcast transmissions over receiver-based multi-channel WMNs. Simulation results over NS-2 network simulator reveal that our proposed hybrid tree-based protocol achieves much higher performance than the utilization of the original receiver-based CA and TBR protocol.

Multicast delivery in heterogeneous wireless networks requires careful coordination, in order to take full advantage of the resources such an interworking network environment can offer. Effective coordination, however, may require interworking signaling from coordinating network entities to receivers of a multicast service. Scalable delivery of such signaling is of great importance, since a large number of receivers may be interested in a multicast service. This paper therefore investigates the use of a multicast signaling channel (MSCH) to carry such interworking signaling in a scalable manner. Applications of interworking signaling for multicast service delivery in heterogeneous wireless networks are presented, motivating the need for an MSCH. Then a comparative study is performed analysing potential benefits of employing an MSCH for signaling message delivery compared to conventional unicast signaling. The analysis reveals that the benefits of the MSCH depend mainly on the selection of an appropriate signaling network to carry the MSCH and also on efficient addressing of a subset of receivers within the MSCH. Based on the findings, guidelines for the selection of a suitable signaling network are provided. Furthermore a novel approach is proposed that allows efficient addressing of a subset of receivers within a multicast group. The approach minimizes the required signaling load on the MSCH by reducing the size of the required addressing information. This is achieved by an aggregation of receivers with common context information. To demonstrate the concept, a prototype of the MSCH has been developed and is presented in the paper.

In this paper, a new subspace-based speech enhancement algorithm is presented. First, we construct a perceptual filterbank from psycho-acoustic model and incorporate it in the subspace-based enhancement approach. This filterbank is created through a five-level wavelet packet decomposition. The masking properties of the human auditory system are then derived based on the perceptual filterbank. Finally, the prior SNR and the masking threshold of each critical band are taken to decide the attenuation factor of the optimal linear estimator. Five different types of in-car noises in TAICAR database were used in our evaluation. The experimental results demonstrated that our approach outperformed conventional subspace and spectral subtraction methods.

We propose the "Two-Step Search scheme with Linear search based Second step (TSS-LS)" by improving the conventional "Two-Step Search scheme with Bit reversal search based Second step (TSS-BS)" for reliable as well as rapid acquisition of Ultra Wide Band (UWB) signals in multipath channels. The proposed TSS-LS utilizes two different thresholds and search windows to achieve fast acquisition. Furthermore, unlike the TSS-BS in which the bit reversal algorithm is applied in both steps, the linear search is adopted for the second step in the proposed TSS-LS to correctly find the starting point in the range of effective delay spread of the multipath channels, and to obtain reliable bit error rate performance of the UWB systems.

In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.

To improve the channel estimation accuracy of multiple-input multiple-output (MIMO) multiplexing, we previously proposed iterative QR-decomposition with M-algorithm (QRD-M) with decision directed channel estimation. In this paper, to keep the computational complexity low while further improving the transmission performance, we will modify previously proposed iterative QRD-M by incorporating cyclic redundancy check (CRC) coding. In the proposed method, transmitted signals are ranked according to their results of CRC decoding and the received signal-to-interference plus noise power ratio (SINR). In the modified M-algorithm, since the results of Turbo decoding and CRC decoding are used to generate the surviving symbol replica, the accuracy of signal detection in the following steps can be improved. Furthermore, based on the results of CRC decoding, iterative process can be terminated before reaching the maximum allowable number of iterations. Computer simulation results show that the loss in the required average received signal energy per bit-to-noise power spectrum density ratio Eb/N0 for average packet error rate (PER) = 10-2 is only about 0.4 dB from maximum likelihood detection (Full MLD) with ideal channel estimation.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

A new method of cancellation of IM3 using current feedback has been proposed for a multi-stage RFIC amplifier. In order to cancel the IM3 present in an output signal of the amplifier, the IIP3 level and IM3 phase of the amplifier are adjusted by means of feedback circuit techniques, so that the target specification is satisfied. By estimating the IIP3 level and IM3 phase variations for two states in situations with and without feedback possessing linear factors, the parameters of a feedback circuit can be calculated. To confirm the validity of the method, we have investigated two approaches; one including an analytical approach to designing a two-stage feedback amplifier, achieving an IIP3 level improvement of 14.8 dB. The other method involves the fabrication of single-stage amplifiers with and without feedback, operating at 850 MHz, both of which were designed as an integrated circuit using a 0.18 µm SiGe BiCMOS process. The fabricated IC's were tested using a load-pull measurement system, and a good agreement between the estimated and measured IIP3 level and IM3 phase variations has been achieved. Further studies show that the error in these variations, as estimated by the method, has been found to be less than 1.5 dB and 15 degrees, respectively, when the load admittance at 1701 MHz was greater than 1/50 S.

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

A new radio-frequency (RF) radiated immunity/susceptibility test method using four-septum TEM cell is proposed. A rotating-EM field can be generated inside the cell by feeding four-different RF DSB-SC signals to four septa arranged in the cell. Since a polarization plane of the rotating-EM field rotates in a low speed, the immunity/susceptibility test for the EM field with various polarizations can be conducted more easily. In this paper, a technique for generating the rotating-EM field in the cell is investigated. The basic characteristics of the cell and the rotating-EM field by using the technique are clarified. To verify the validity of this test method, a RF radiated susceptibility of a printed circuit board is measured. The measured results are verified by comparing with the theoretical results based on modified telegrapher's equations.

Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-µm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300 MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.