The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

Blind signatures allow a signer to digitally sign a document without being able to glean any information about the document. In this paper, we investigate the symmetric analog of blind signatures, namely blind message authentication codes (blind MACs). One may hope to get the same efficiency gain from blind MAC constructions as is usually obtained when moving from asymmetric to symmetric cryptosystems. Our main result is a negative one however: we show that the natural symmetric analogs of the unforgeability and blindness requirements cannot be simultaneously satisfied. Faced with this impossibility, we show that blind MACs do exist (under the one-more RSA assumption in the random oracle model) in a more restrictive setting where users can share common state information. Our construction, however, is only meant to demonstrate the existence; it uses an underlying blind signature scheme, and hence does not achieve the desired performance benefits. The construction of an efficient blind MAC scheme in this restrictive setting is left as an open problem*.

Ring signature scheme enables a signer to sign a message anonymously. In the ring signature scheme, the signer who wants to sign a document anonymously first chooses some public keys of entities (signers) and then generates a signature which ensures that one of the signer or entities signs the document. In some situations, however, the ring signature scheme allows the signer to shift the blame to victims because of the anonymity. The group signature scheme may be a solution for the problem; however, it needs an electronic big brother, called a group manager, who can violate the signer anonymity by himself, and a complicated key setting. This paper introduces a new notion of a signature scheme with signer anonymity, a deniable ring signature scheme (DRS), in which no group manager exists, and the signer should be involved in opening the signer anonymity. We also propose a concrete scheme proven to be secure under the assumption of the DDH (decision Diffie Hellman) problem in the random oracle model.

A tri-template-based codes (TTBC) method is proposed to reduce test cost of intellectual property (IP) cores. In order to reduce test data volume (TDV), the approach utilizes three templates, i.e., all 0, all 1, and the previously applied test data, for generating the subsequent test data by flipping the inconsistent bits. The approach employs a small number of test channels I to supply a large number of internal scan chains 2I-3 such that it can achieve significant reduction in test application time (TAT). Furthermore, as a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is suitable for IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT and the given test set. Theoretical analysis and experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

Recently, system level design languages (SLDLs), which can describe both hardware and software aspects of the design, are receiving attentions. Analog mixed-signal (AMS) extensions to SLDLs enable current discrete-oriented SLDLs to describe and simulate not only digital systems but also digital-analog mixed-signal systems. In this paper, we present our work on the AMS extension to one of the system level design language--SpecC. The extended language supports designer to describe all the analog, digital and software aspects in a universal language.

A nonlinear optical fiber loop mirror (NOLM) adapted for all-optical 2R operation at ultrahigh bit-rates was experimentally and theoretically investigated. The proposed NOLM was created by adding inline/external fiber polarizers and also an inline optical phase-bias compensator (OPBC) to a standard NOLM. A theoretical investigation revealed that the operation of the standard NOLM became unstable due to residual polarization crosstalk of the polarization-maintaining optical components making up the NOLM, and that it could be dramatically improved with the inline/external polarizers. The NOLM with the polarizers ensured stable switching operation with high switching-dynamic-range (>30 dB) against the change of the wavelength of the input clock pulses, and the change of the environment temperature. We also experimentally verified that the OPBC played a dramatic role to ensure excellent dynamic switching performance of the NOLM, and to achieve signal-Q-recovery of the regenerated signals. All optical 2R experiments at 40 Gb/s and 160 Gb/s were performed with the modified NOLM. Signal regeneration with improved extinction ratio and signal Q value was successfully demonstrated. Q-recovery to the input of the control pulses degraded with ASE noise accumulation was also successfully achieved.

We previously proposed an architecture for software defined radio called the reconfigurable packet routing-oriented signal processing platform (RPPP). This architecture was suited to wireless signal processing applications, which require radio functions to be selected in real time depending on the transmitted signal. A number of radio standards are used in DSRC systems for vehicle communication and vehicle equipment is required to transmit and receive the radio signals used on each particular occasion. An implementation of RPPP is described in this paper that enables the dynamic handling of two ARIB standards for DSRC. After an explanation of the basic architecture and an analysis of RPPP, the implementation of a reconfigurable DSRC transceiver for ASK and π/4 shift-QPSK is described. The implementation is then discussed, evaluated in terms of the number of logic units needed. We concluded that our platform is 27.6% more efficient in utilizing logic than that achieved with fixed design.

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.

A unified representation for various kinds of speculations and global scheduling algorithms is presented. After introducing several types of local and global speculations, reviewing our conventional method called conditional vector-based list scheduling, and discussing some of its limitations, we introduce the unique notion of generalized condition vectors (GCVs), which can represent most varieties of speculations and multiple branches as a single vector. The unification of parallel branches and partially unresolved nested conditional branches is discussed. Then, a scheduling algorithm using GCVs is proposed. Experimental results show the effectiveness of the GCV-based scheduling method.

Combinatorial designs have been used to construct digital fingerprint codes. Here, a new constructive algorithm for an anticollusion fingerprint code based on group-divisible designs is presented. These codes are easy to construct and available for a large number of individuals, which is important from a business point of view. Group-divisible designs have not been used previously as a tool for fingerprint code construction.

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.

A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.

This paper proposes a network design scheme for Virtual Private Network (VPN) services. Traditionally, network design to compute required amount of resource is based on static point-to-point resource demand. This scheme is effective for traditional private line services. However, since VPN services allow multi-site connectivity for customers, it may not be appropriate to design a network based on static point-to-point resource demand. In particular, this scheme is not effective when the traffic pattern changes over time. Therefore, network design for VPN services introduces a new challenge in order to comply with traffic flexibility. There are conventional studies tackling this issue. In those studies, by defining a resource demand model considering flexibility, and designing the network based on this model, amount of resource required can be computed. However, there are some deficiencies in those studies. This paper proposes a new network design scheme, consisting of two components. The first one is a new resource demand model, created by extending conventional resource demand models, that can specify resource demand more precisely. The second one is a new network design algorithm for this resource demand model. Simulations are conducted to evaluate the performance of the proposed network design scheme, and the results show significant performance improvement against conventional schemes. In addition, deployment considerations of the proposed scheme are analyzed.

This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.

This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented.

This paper presents a semi-blind algorithm for multiuser interference cancellation and fading amplitude estimation for downlink MIMO DS-CDMA systems with multipath fading channels. Taking advantage of the space-time information of the parametric multipath channel, the proposed algorithm first uses a space-time channel decoupler to suppress multiuser interference and then decomposes the channel into a set of parallel subchannels each containing the signal of the desired user on an individual multipath. Two criteria, the complementary orthogonal projection (COP) and the minimum variance distortionless response (MVDR), are employed by the space-time decoupler to achieve interference suppression and signal separation. The fading amplitudes can then be estimated from the eigen space of the output of the space-time channel decoupler. It follows that the signal of interest can be maximally combined in a pathwise manner and then differentially decoded.

In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.

Synchronous sampling allows alternating current (AC) quantities, such as the root mean square (RMS) values of voltage and power, to be determined with very low uncertainties (on the order of a few parts of 10-6 [1]). In this paper, a mathematical expression for estimating measurement uncertainties in nonideal synchronization with fundamental frequency AC signals is presented. The obtained results were compared with those obtained by measurements with a high-precision instrument used for measuring basic AC values.

In this paper, we compare two signal designs for uplink quasi-synchronous code division multiple access (CDMA) channels in order to optimize the trade-off between bandwidth efficiency and power efficiency. The design we call band-limited DS/CDMA design, is based on the time-domain assignment of Gold sequences, just as in the ordinary DS/CDMA, but with band-constrained cyclic chip interpolation functions, which is unlike the ordinary DS/CDMA. The other design, MC/CDMA design, is based on frequency-domain assignment of the sequences, as in the ordinary MC/CDMA. In both designs, we assume insertion of guard intervals at the transmitter and frequency-domain processing in reception. Assuming quasi-synchronous arrival of CDMA signals at the CDMA base station and FFT in the effective symbol interval, the intersymbol interference is evaded in both designs. First we identified the signal parameters that optimize bandwidth efficiency in each of the band-limited DS design and MC design. Second, we clarified the signal parameters that optimize the power efficiency as functions of frequency efficiency in each of the two designs. Finally, we derived and compared the trade-off between the bandwidth efficiency and power efficiency of band-limited DS and MC designs. We found a superiority of band-limited DS design over MC design with respect to the optimized trade-off.