This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

This paper presents a semi-blind algorithm for multiuser interference cancellation and fading amplitude estimation for downlink MIMO DS-CDMA systems with multipath fading channels. Taking advantage of the space-time information of the parametric multipath channel, the proposed algorithm first uses a space-time channel decoupler to suppress multiuser interference and then decomposes the channel into a set of parallel subchannels each containing the signal of the desired user on an individual multipath. Two criteria, the complementary orthogonal projection (COP) and the minimum variance distortionless response (MVDR), are employed by the space-time decoupler to achieve interference suppression and signal separation. The fading amplitudes can then be estimated from the eigen space of the output of the space-time channel decoupler. It follows that the signal of interest can be maximally combined in a pathwise manner and then differentially decoded.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.

A family of sequences with zero correlation zone, which is shortly called a ZCZ set, can provide CDMA system without co-channel interference nor influence of multipath. This paper presents two types of ZCZ sets of non-binary sequence pairs, which achieve the upper bound of family size for length and zero correlation zone. One, which is produced by use of a perfect complementary pair and an orthogonal code, can change zero correlation zone, while the upper bound is kept. The other, which is generated by use of a newly defined orthogonal pair and an orthogonal code, can offer such CDMA system as a binary ZCZ set seems to be used.

The decorrelating detector is one of the detecting methods in a direct sequence code division multiple access systems. We investigate the blind adaptive decorrelating detector (BADD) using only the signature of the desired user (DU) according to the assumption that the algorithm is used in downlink. When the BADD is constructed with an antenna array, both the spatial and temporal signature must be taken into consideration for signal detection. We propose the BADD incorporated with the blind estimation of spatial signature (SS) of the DU only from the received signals. As the estimation procedure of SS, the orthogonal projection approximation and subspace tracking algorithm is adopted. The proposed BADD presented the BER improvement with using antenna array. The BER performance has a lower limit with increasing the number of antenna array elements.

A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.

A new fast and reliable image objective quality evaluation technique is presented in this paper. The proposed method takes image structure into account and uses a low complexity homogeneity measure to evaluate the intensity uniformity of a local region based on high-pass operators. We experimented with monochrome images under different types of distortions. Experimental results indicate that the proposed method provides better consistency with the perceived image quality. It is suitable for real applications to control the processed image quality.

An alternative human interface enabling the handicapped with severe motor disabilities to control an assistive system is presented. Since this interface relies on the biosignals originating from the contraction of muscles on the face during particular movements, even individuals with a paralyzed limb can use it with ease. For real-world application, a dedicated hardware module employing a general-purpose DSP was implemented and its validity tested on an electrically powered wheelchair. Furthermore, an additional attempt to reduce error rates to a minimum for stable operation was also made based on the entropy information inherent in the signals during the classification phase. In the experiments in which 11 subjects participated, it was found most of them could control the target system at their own will, and thus the proposed interface could be considered a potential alternative for the interaction of the severely handicapped with electronic systems.

Recently, Waters proposed a provably secure signature schemes in the standard model. In this letter, we analyse the security of this signature scheme. We found that the signature scheme is subjected to key substitution attack and is malleable.

This paper presents two kinds of new ZCZ codes consisting of trios of two binary sequences and a bi-phase sequence, which can reach the upper bound on the ZCZ codes. From the viewpoint of sequence design, it is shown that they can provide the most effective ASK-CDMA system, which can remove co-channel interference.

This paper presents constructions of two kinds of sets of sequences with a zero correlation zone, called ZCZ code, which can reach the upper bound of the member size of the sequence set. One is a ZCZ code which can be constructed by a unitary matrix and a perfect sequence. Especially, a ternary perfect sequence with elements 1 and zero can be used to construct the proposed ZCZ code. The other is a ZCZ code of pairs of ternary sequences and binary sequences which can be constructed by an orthogonal matrix that includes a Hadamard matrix and an orthogonal sequence pair. As a special case, an orthogonal sequence pair, which consists of a ternary sequence and a binary sequence, can be used to construct the proposed ZCZ code. These codes can provide CDMA systems without co-channel interference.

In this article, the empirical mode decomposition (EMD) is introduced to the problem of signal detection in underwater sound. EMD is a new method pioneered by Huang et al. for non-linear and non-stationary signal analysis. Based on the EMD, any input data can be decomposed into a small number of intrinsic mode functions (IMFs) which can serve as the basis of non-stationary data for they are complete, almost orthogonal, local and adaptive. Another useful tool for processing transient signals is discrete wavelet transform (DWT). In this paper, these IMFs are applied to determine when the particular signals appear. From the computer simulation, based on the receiver operating characteristics (ROC), a performance comparison shows that this proposed EMD-based detector is better than the DWT-based method.

Binary sequences with two-level periodic autocorrelation correspond directly to cyclic (v, k, λ)-designs. When v = 4t-1, k = 2t -1 and λ = t-1, for some positive integer t, the sequence (or design) is called a cyclic Hadamard sequence (or design). For all known examples, v is either a prime number, a product of twin primes, or one less than a power of 2. Except when v = 2k-1, all known examples are based on quadratic residues (using the Legendre symbol when v is prime, and the Jacobi symbol when v = p(p+2) where both p and p+2 are prime); or sextic residues (when v is a prime of the form 4a2 + 27). However, when v = 2k-1, many constructions are now known, including m-sequences (corresponding to Singer difference sets), quadratic and sextic residue sequences (when 2k-1 is prime), GMW sequences and their generalizations (when k is composite), certain term-by-term sums of three and of five m-sequences and more general sums of trace terms, several constructions based on hyper-ovals in finite geometries (found by Segre, by Glynn, and by Maschietti), and the result of performing the Welch-Gong transformation on some of the foregoing.

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant nn Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i+1)-th slices. Since the i-th slice has a similar structure to the (i+1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 3232 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.

Some signal design methods for the approximately synchronized CDMA systems based on complete complementary codes have been proposed. It has been shown that estimating the multipath channels and applying the convolution of the spread signals can increase both the information transmission rate and frequency usage efficiency. There are some variations of such signal design methods using complete complementary codes. The efficiency of the communication systems and information transmission rate depend upon the applied signal design method and the modulation scheme. In this paper, we consider two of these signal design methods. We analyze the bit error rate (BER) performances for both methods through some numerical simulations under the single cell scenario. Numerical results show the BER properties under some modulation schemes such as BPSK, QPSK and 16QAM. Some discussions on the relation between the BER performance and the information transmission rate are also included.

The optical network represents a promising approach to achieve a scalable backbone network. In backbone networks, survivability is important because high volumes of traffic are prone to be damaged by faulty equipment. Various design methods for survivable optical networks have been proposed, although none considering the simultaneous maintenance of multiple transmission lines has been proposed to our knowledge. This paper proposes a design method for survivable optical networks where multiple transmission lines sharing common transmission equipment may suffer simultaneous damage, due to failure in the transmission equipment. Moreover, two transmission lines can be maintained simultaneously. A mathematical programming model to obtain the optimum lightpath arrangement is presented assuming three kinds of lightpath recovery schemes. The relation between the required transmission line capacity and the combination pattern of two transmission lines that undergo maintenance is clarified using the proposed design method.

In the optimum design of contactors, it is important to analyze the dynamic behaviors. In this paper, it proposes a new computational approach for analyzing dynamic characteristic of the energy-saving and bouncing-reducing double-coil contactor. According to the contactor's unique characteristic that it has two transferable coils, the paper builds two different sets of equations. One describes the period before the transfer position, and the other describes the period after the transfer position. The equations deal with the electrical circuit, electromagnetic field that can be calculated by using 3-D finite element method and mechanical system considering the influence of friction. The validity of the proposed method is confirmed by experiment. Finally, the paper gives an optimum design for the transfer position of the two coils. The result of the optimum design reduces both of the first and the second bounces of the movable contact.

The recognition vector of the decision-theoretic approach and that of cumulant-based classification are combined to compose a higher dimension hyperspace to get the benefits of both methods. The method proposed in this paper can cover more kinds of signals including signals with order higher than 4 in the AWGN channel even under low SNR values, i.e. those down to -5 dB. The composed vector is input into an RBF neural network to get more reasonable reference points. Eleven kinds of signals, say 2ASK, 4ASK, 8ASK, 2PSK, 4PSK, 8PSK, 2FSK 4FSK, 8FSK, 16QAM and 64QAM, are involved in the discussion.

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 µm CMOS technology.