In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.

Wireless sensor nodes are becoming more and more common in various settings and require a long battery life for better maintainability. Since most sensor nodes are powered by batteries, energy efficiency is a critical problem. In an experiment, we observed that when peak power consumption is high, battery voltage drops quickly, and the sensor stops working even though some useful charge remains in the battery. We propose three off-line algorithms that extend battery life by scheduling sensors' execution time that is able to reduce peak power consumption as much as possible under a deadline constraint. We also developed a simulator to evaluate the effectiveness of these algorithms. The simulation results showed that one of the three algorithms dramatically can extend battery life approximately three time as long as in simultaneous sensor activation.

In maritime networks, the communication links are characterized as high dynamics due to ship mobility and fluctuation of the sea surface. The performance of traditional transmission protocols is poor in maritime networks. Thus, some researchers have considered using Delay Tolerant Network (DTN) to improve the performance of data transmission in maritime environment. Most existing work on maritime DTNs uses simulation to evaluate the transmission performance in maritime DTNs. In this paper, we develop a theoretical model to analyze the performance of data transmission in maritime DTNs. We first construct a model to describe the ship encounter probability. Then, we use this model to analyze the data delivery ratio from ships in the seaway to the base station (BS) on the coast. Based on the data of tracing the ships navigating in a realistic seaway, we develop a simulator and validate the theoretical models. In addition, by comparing the performance of DTN transmission protocol and traditional end-to-end transmission protocol, we confirm that DTN protocol can effectively improve the performance of data transmission in maritime networks.

Cognitive beamforming exploiting spatial opportunity is an attractive technique for secondary users to coexist with primary users in cognitive radio environments. If perfect channel state information of the interfering link is available, interference from a secondary transmitter to a primary receiver can be perfectly pre-nulled by choosing the ideal transmit beam. In practice, however, there is channel estimation error due to noise and the time-varying channels. To minimize the residual interference due to those channel estimation errors, channel prediction based on auto regressive (AR) model is introduced in this paper. Further, to cope with extremely rapidly-varying channels, a cognitive transmit power control technique is proposed as well. By combining channel prediction and transmit power control in cognitive beamforming, the cognitive users can share the spectrum with the primary users with a limited interference level in time-varying channels.

It is well known that cognitive radio (CR) techniques have great potential for supporting future demands on the scarce radio spectrum resources. For example, by enabling the utilization of spectrum bands temporarily not utilized by primary users (PUs) licensed to operate on those bands. Spectrum sensing is a well-known CR technique for detecting those unutilized bands. However, the spectrum sensing outcomes cannot be perfect and there will always be some misdetections and false alarms which will affect the performance thereby degrading the quality of service (QoS) of PUs. Continuous time Markov chain (CTMC) based modeling has been widely used in the literature to evaluate the performance of CR networks (CRNs). A major limitation of the available literature is that all the key factors and realistic elements such as the effect of imperfect sensing and state dependent transition rates are not modeled in a single work. In this paper, we present a CTMC based model for analyzing the performance of CRNs. The proposed model differs from the existing models by accurately incorporating key elements such as full state dependent transition rates, multi-channel support, handoff capability, and imperfect sensing. We derive formulas for primary termination probability, secondary success probability, secondary blocking probability, secondary forced termination probability, and radio resource utilization. The results show that incorporating fully state dependent transition rates in the CTMC can significantly improve analysis accuracy, thus achieving more realistic and accurate analytical model. The results from extensive Monte Carlo simulations confirm the validity of our proposed model.

Scale Invariant Feature Transform (SIFT) algorithm is a very excellent approach for feature detection. It is characterized by data intensive computation. The current studies of accelerating SIFT algorithm are mainly reflected in three aspects: optimizing the parallel parts of the algorithm based on general-purpose multi-core processors, designing the customized multi-core processor dedicated for SIFT, and implementing it based on the FPGA platform. The real-time performance of SIFT has been highly improved. However, the factors such as the input image size, the number of octaves and scale factors in the SIFT algorithm are restricted for some solutions, the flexibility that ensures the high execution performance under variable factors should be improved. This paper proposes a reconfigurable solution to solve this problem. We fully exploit the algorithm and adopt several techniques, such as full parallel execution, block computation and CORDIC transformation, etc., to improve the execution efficiency on a REconfigurable MUltimedia System called REMUS. Experimental results show that the execution performance of the SIFT is improved by 33%, 50% and 8 times comparing with that executed in the multi-core platform, FPGA and ASIC separately. The scheme of dynamic reconfiguration in this work can configure the circuits to meet the computation requirements under different input image size, different number of octaves and scale factors in the process of computing.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

In order to support the increasing amount of mobile data traffic, Third Generation Partnership Project (3GPP) is actively discusses cell range expansion (CRE) and time domain multiplexing – inter-cell interference coordination (TDM-ICIC). They have shown to be attractive techniques for heterogeneous network (HetNet) deployment where pico base stations (BSs) overlay macro BSs. There are two control schemes of the TDM-ICIC. One, named ZP-scheme, stops radio resource assignments for data traffic in predetermined radio resources in the time domain (subframes). The other, named RP-scheme, maintains the resource assignment whereas it reduces the transmission power at macro BSs at predetermined subframes. In this paper, we clarify the effective ranges of both ZP-scheme and RP-scheme by conducting the system level simulations. Moreover, the appropriate power reduction value at predetermined subframes is also clarified from the difference in the effective range of various power reduction values. The comprehensive evaluation results show that both ZP-scheme and RP-scheme are not effective when the CRE bias value is 0 dB or less. If the CRE bias value is larger than 0 dB, they are effective when the ratio of predetermined subframes in all subframes is set to appropriate values. These values depend on the CRE bias value and power reduction in the predetermined subframes. The effective range is expanded when the power reduction in the predetermined subframes changes with the CRE bias value. Therefore, the effective range of RP-scheme is larger than that of ZP-scheme by setting an appropriate power reduction in the predetermined subframes.

An instrumental variable (IV) based linear estimator is proposed for effective target localization in sensor network by using time-difference-of-arrival (TDOA) measurement. Although some linear estimation approaches have been proposed in much literature, the target localization based on TDOA measurement still has a room for improvement. Therefore, we analyze the estimation errors of existing localization estimators such as the well-known quadratic correction least squares (QCLS) and the robust least squares (RoLS), and demonstrate advantages of the proposition by comparing the estimation errors mathematically and showing localization results through simulation. In addition, a recursive form of the proposition is derived to consider a real time application.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

Initial cell search in wideband code-division multiple-access (W-CDMA) systems is a challenging process. On the one hand, channel impairments such as multipath fading, Doppler shift, and noise create frequency and time offsets in the received signal. On the other hand, the residual synchronization error of the crystal oscillator at the mobile station also causes time and frequency offsets. Such offsets can affect the ability of a mobile station to perform cell search. Previous work concentrated on cell synchronization algorithms that considered multipath channels and frequency offsets, but ignored clock and timing offsets due to device tolerances. This work discusses a robust initial cell search algorithm, and quantifies its performance in the presence of frequency and time offsets due to two co-existing problems: channel impairments and clock drift at the receiver. Another desired performance enhancement is the reduction of power consumption of the receiver, which is mainly due to the computational complexity of the algorithms. This power reduction can be achieved by reducing the computational complexity by a divide and conquer strategy during the synchronization process.

A precoding design for double space-time block coding (STBC) system is investigated in this paper, i.e., the joint processing of STBC and dirty paper coding (DPC) techniques. These techniques are used for avoiding dual spatial streams interference and improving the transmitter diversity. The DPC system is interference free on multi-user or multi-antenna. The STBC transceiver can provide the transmit diversity. Due to the benefits about offered by the STBC and DPC techniques, we propose a new scheme called STBC-DPC system. The transceiver design involves the following procedures. First, the ordering QR decomposition of channel matrix and the maximum likelihood (ML) one-dimensional searching algorithm are proposed to acquire reliable performance. Next, the channel on/off assignment using the water filling algorithm, i.e., maximum capacity criterion, is proposed to overcome the deep fading channel problem. Finally, the STBC-DPC system with the modulus operation to limit the transmit signal level, i.e., the Tomlinson-Harashima precoding (THP) scheme, is proposed to achieve low peak-to-average power ratio (PAPR) performance. Simulation results confirm that the proposed STBC-DPC/THP with water filling ML algorithm can provide the low PAPR and excellent bit error rate (BER) performances.

As a flexible and cost-efficient scalable Internet access network, we studied architectures, protocols, and design optimizations of the Wireless Internet-access Mesh NETwork (WIMNET). WIMNET is composed of multiple access points (APs) connected through multihop wireless communications on IEEE 802.11 standards. The increasing popularity of real-time applications such as IP-phones and IP-TV means that they should be supported in WIMNET. However, the contention resolution mechanism using a random backoff-time in the CSMA/CA protocol of 802.11 standards is not sufficient for handling real-time traffic in multihop wireless communications. In this paper, we propose a Fixed Backoff-time Switching (FBS) method for the CSMA/CA protocol to improve the real-time traffic performance in WIMNET by giving the necessary activation chances to each link. We implement our proposal on the QualNet simulator, and verify its effectiveness through simulations on three network topologies with four scenarios.

In this paper, we study decentralized supervisory control of timed discrete event systems, where we adopt the OR rule for fusing local enablement decisions and the AND rule for fusing local enforcement decisions. For any specification language satisfying a certain assumption, we propose a method for constructing a decentralized supervisor that achieves its sublanguage. The proposed method does not require computing the achieved sublanguage.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 µW, which was only 3.261% that of a conventional multimedia processor.

We address the global asymptotic stability of FAST TCP, especially considering cross traffics, time-varying network feedback delay, and queuing delay dynamics at link. Exploiting the inherent dynamic property of FAST TCP, we construct two sequences that represent the lower and upper bound variations of the congestion window in time. By showing that the sequences converge to the equilibrium point of the congestion window, we establish that FAST TCP in itself is globally asymptotically stable without any specific conditions on the tuning parameter α or the update gain γ.

REMUS-II (REconfigurable MUltimedia System 2) is a coarse-grained dynamically reconfigurable computing system for multimedia and communication baseband processing. This paper proposes a real-time H.264 baseline profile encoder on REMUS-II. First, we propose an overall mapping flow for mapping algorithms onto the platform of REMUS-II system and then illustrate it by implementing the H.264 encoder. Second, parallel and pipelining techniques are considered for fully exploiting the abundant computing resources of REMUS-II, thus increasing total computing throughput and solving high computational complexity of H.264 encoder. Besides, some data-reuse schemes are also used to increase data-reuse ratio and therefore reduce the required data bandwidth. Third, we propose a scheduling scheme to manage run-time reconfiguration of the system. The scheduling is also responsible for synchronizing the data communication between tasks and handling conflict between hardware resources. Experimental results prove that the REMUS-MB (REMUS-II version for mobile applications) system can perform a real-time H.264/AVC baseline profile encoder. The encoder can encode CIF@30 fps video sequences with two reference frames and maximum search range of [-16,15]. The implementation, thereby, can be applied to handheld devices targeted at mobile multimedia applications. The platform of REMUS-MB system is designed and synthesized by using TSMC 65 nm low power technology. The die size of REMUS-MB is 13.97 mm2. REMUS-MB consumes, on average, about 100 mW while working at 166 MHz. To my knowledge, in the literature this is the first implementation of H.264 encoding algorithm on a coarse-grained dynamically reconfigurable computing system.

PREIMAGE CONSTRUCTION problem by Kratsch and Hemaspaandra naturally arose from the famous graph reconstruction conjecture. It deals with the algorithmic aspects of the conjecture. We present an O(n8) time algorithm for PREIMAGE CONSTRUCTION on permutation graphs and an O(n4(n+m)) time algorithm for PREIMAGE CONSTRUCTION on distance-hereditary graphs, where n is the number of graphs in the input, and m is the number of edges in a preimage. Since each graph of the input has n-1 vertices and O(n2) edges, the input size is O(n3) (, or O(nm)). There are polynomial time isomorphism algorithms for permutation graphs and distance-hereditary graphs. However the number of permutation (distance-hereditary) graphs obtained by adding a vertex to a permutation (distance-hereditary) graph is generally exponentially large. Thus exhaustive checking of these graphs does not achieve any polynomial time algorithm. Therefore reducing the number of preimage candidates is the key point.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.