The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] (42807hit)

11401-11420hit(42807hit)

  • Energy-Efficient Adaptive Virtual MIMO Transmission in a Transmit-Side Correlated Wireless Sensor Network

    Jaehyun PARK  Byung Jang JEONG  

     
    PAPER-Network

      Vol:
    E96-B No:4
      Page(s):
    976-985

    In this paper, performances of two different virtual multiple-input multiple-output (MIMO) transmission schemes — spatial multiplexing (SM) and space-time block coding (STBC) — in a correlated wireless sensor network are analyzed. By utilizing a complex Wishart distribution, we investigate the statistical properties of a correlated virtual MIMO channel between the sensors and data collector that is used in the performance analysis of each MIMO transmission mode. Distributed sensors then transmit their data cooperatively to the data collector by choosing a proper transmission mode adaptively based on the channel conditions and spatial correlation among the sensors. Furthermore, after analyzing the energy efficiencies of SM and STBC, we propose a new energy efficient mode switching rule between SM and STBC. Finally, by analytically deriving the required transmit energy of the proposed adaptive transmission scheme, the manner in which the spatial correlation influences the energy consumption is shown. This suggests a cooperating node scheduling protocol that makes energy consumption less sensitive to the variation of the spatial correlation.

  • Efficient Shared Protection Network Design Algorithm that Iterates Path Relocation with New Resource Utilization Metrics

    Masakazu SATO  Hiroshi HASEGAWA  Ken-ichi SATO  

     
    PAPER-Fiber-Optic Transmission for Communications

      Vol:
    E96-B No:4
      Page(s):
    956-966

    We propose an efficient network design algorithm that realizes shared protection. The algorithm iteratively improves the degree of wavelength resource usage and fiber utilization. To achieve this, we newly define two metrics to evaluate the degree of wavelength resource usage of a pair of working/backup paths and the fiber utilization efficiency. The proposed method iteratively redesigns groups of paths that are selected in the order determined by the metrics. A numerical analysis verifies that the proposed algorithm can substantially reduce the required wavelength resources and hence fiber cost. It is also verified that the computational complexity of the proposed algorithm is small enough to terminate within practicable time.

  • Automated Ulcer Detection Method from CT Images for Computer Aided Diagnosis of Crohn's Disease Open Access

    Masahiro ODA  Takayuki KITASAKA  Kazuhiro FURUKAWA  Osamu WATANABE  Takafumi ANDO  Hidemi GOTO  Kensaku MORI  

     
    PAPER-Medical Image Processing

      Vol:
    E96-D No:4
      Page(s):
    808-818

    Crohn's disease commonly affects the small and large intestines. Its symptoms include ulcers and intestinal stenosis, and its diagnosis is currently performed using an endoscope. However, because the endoscope cannot pass through the stenosed parts of the intestines, diagnosis of the entire intestines is difficult. A CT image-based method is expected to become an alternative way for the diagnosis of Crohn's disease because it enables observation of the entire intestine even if stenosis exists. To achieve efficient CT image-based diagnosis, diagnostic-aid by computers is required. This paper presents an automated detection method of the surface of ulcers in the small and large intestines from fecal tagging CT images. Ulcers cause rough surfaces on the intestinal wall and consist of small convex and concave (CC) regions. We detect them by blob and inverse-blob structure enhancement filters. A roughness value is utilized to reduce the false positives of the detection results. Many CC regions are concentrated in ulcers. The roughness value evaluates the concentration ratio of the detected regions. Detected regions with low roughness values are removed by a thresholding process. The thickness of the intestinal lumen and the CT values of the surrounding tissue of the intestinal lumen are also used to reduce false positives. Experimental results using ten cases of CT images showed that our proposed method detects 70.6% of ulcers with 12.7 FPs/case. The proposed method detected most of the ulcers.

  • Classification of Pneumoconiosis on HRCT Images for Computer-Aided Diagnosis Open Access

    Wei ZHAO  Rui XU  Yasushi HIRANO  Rie TACHIBANA  Shoji KIDO  Narufumi SUGANUMA  

     
    PAPER-Computer-Aided Diagnosis

      Vol:
    E96-D No:4
      Page(s):
    836-844

    This paper describes a computer-aided diagnosis (CAD) method to classify pneumoconiosis on HRCT images. In Japan, the pneumoconiosis is divided into 4 types according to the density of nodules: Type 1 (no nodules), Type 2 (few small nodules), Type 3-a (numerous small nodules) and Type 3-b (numerous small nodules and presence of large nodules). Because most pneumoconiotic nodules are small-sized and irregular-shape, only few nodules can be detected by conventional nodule extraction methods, which would affect the classification of pneumoconiosis. To improve the performance of nodule extraction, we proposed a filter based on analysis the eigenvalues of Hessian matrix. The classification of pneumoconiosis is performed in the following steps: Firstly the large-sized nodules were extracted and cases of type 3-b were recognized. Secondly, for the rest cases, the small nodules were detected and false positives were eliminated. Thirdly we adopted a bag-of-features-based method to generate input vectors for a support vector machine (SVM) classifier. Finally cases of type 1,2 and 3-a were classified. The proposed method was evaluated on 175 HRCT scans of 112 subjects. The average accuracy of classification is 90.6%. Experimental result shows that our method would be helpful to classify pneumoconiosis on HRCT.

  • An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation

    Minoru IIZUKA  Naohiro HAMADA  Hiroshi SAITO  

     
    PAPER

      Vol:
    E96-C No:4
      Page(s):
    482-491

    This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.

  • Cell Search Synchronization under the Presence of Timing and Frequency Offsets in W-CDMA

    Wisam K. HUSSAIN  Loay D. KHALAF  Mohammed HAWA  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E96-B No:4
      Page(s):
    1012-1018

    Initial cell search in wideband code-division multiple-access (W-CDMA) systems is a challenging process. On the one hand, channel impairments such as multipath fading, Doppler shift, and noise create frequency and time offsets in the received signal. On the other hand, the residual synchronization error of the crystal oscillator at the mobile station also causes time and frequency offsets. Such offsets can affect the ability of a mobile station to perform cell search. Previous work concentrated on cell synchronization algorithms that considered multipath channels and frequency offsets, but ignored clock and timing offsets due to device tolerances. This work discusses a robust initial cell search algorithm, and quantifies its performance in the presence of frequency and time offsets due to two co-existing problems: channel impairments and clock drift at the receiver. Another desired performance enhancement is the reduction of power consumption of the receiver, which is mainly due to the computational complexity of the algorithms. This power reduction can be achieved by reducing the computational complexity by a divide and conquer strategy during the synchronization process.

  • Robust Cyclic ADC Architecture Based on β-Expansion

    Rie SUZUKI  Tsubasa MARUYAMA  Hao SAN  Kazuyuki AIHARA  Masao HOTTA  

     
    PAPER

      Vol:
    E96-C No:4
      Page(s):
    553-559

    In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.

  • Fast and Robust 3D Correspondence Matching and Its Application to Volume Registration Open Access

    Yuichiro TAJIMA  Kinya FUDANO  Koichi ITO  Takafumi AOKI  

     
    PAPER-Medical Image Processing

      Vol:
    E96-D No:4
      Page(s):
    826-835

    This paper presents a fast and accurate volume correspondence matching method using 3D Phase-Only Correlation (POC). The proposed method employs (i) a coarse-to-fine strategy using multi-scale volume pyramids for correspondence search and (ii) high-accuracy POC-based local block matching for finding dense volume correspondence with sub-voxel displacement accuracy. This paper also proposes its GPU implementation to achieve fast and practical computation of volume registration. Experimental evaluation shows that the proposed approach exhibits higher accuracy and lower computational cost compared with conventional method. We also demonstrate that the GPU implementation of the proposed method can align two volume data in several seconds, which is suitable for practical use in the image-guided radiation therapy.

  • A New Algorithm for Fused Blocked Pattern Matching

    Hua ZHAO  Songfeng LU  Yan LIU  

     
    LETTER-Algorithms and Data Structures

      Vol:
    E96-A No:4
      Page(s):
    830-832

    Fused Blocked Pattern Matching is a kind of approximate matching based on Blocked Pattern Matching, and can be used in identification of fused peptides in tumor genomes. In this paper, we propose a new algorithm for fused blocked pattern matching. We give a comparison between Julio's solution and ours, which shows our algorithm is more efficient.

  • A Synthesis Method for Decentralized Supervisors for Timed Discrete Event Systems

    Masashi NOMURA  Shigemasa TAKAI  

     
    LETTER-Concurrent Systems

      Vol:
    E96-A No:4
      Page(s):
    835-839

    In this paper, we study decentralized supervisory control of timed discrete event systems, where we adopt the OR rule for fusing local enablement decisions and the AND rule for fusing local enforcement decisions. For any specification language satisfying a certain assumption, we propose a method for constructing a decentralized supervisor that achieves its sublanguage. The proposed method does not require computing the achieved sublanguage.

  • On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems

    Jinmyoung KIM  Toru NAKURA  Koichiro ISHIBASHI  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER

      Vol:
    E96-C No:4
      Page(s):
    560-567

    This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

  • Efficient XML Retrieval Service with Complete Path Representation

    Hsu-Kuang CHANG  King-Chu HUNG  I-Chang JOU  

     
    PAPER-Data Engineering, Web Information Systems

      Vol:
    E96-D No:4
      Page(s):
    906-917

    Compiling documents in extensible markup language (XML) increasingly requires access to data services which provide both rapid response and the precise use of search engines. Efficient data service should be based on a skillful representation that can support low complexity and high precision search capabilities. In this paper, a novel complete path representation (CPR) associated with a modified inverted index is presented to provide efficient XML data services, where queries can be versatile in terms of predicates. CPR can completely preserve hierarchical information, and the new index is used to save semantic information. The CPR approach can provide template-based indexing for fast data searches. An experiment is also conducted for the evaluation of the CPR approach.

  • A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method

    Hyuk-Jun LEE  Seung-Chul KIM  Eui-Young CHUNG  

     
    LETTER-Computer System

      Vol:
    E96-D No:4
      Page(s):
    963-966

    A packet memory stores packets in internet routers and it requires typically RTTC for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to , where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.

  • Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs

    Nan LIU  Song CHEN  Takeshi YOSHIMURA  

     
    PAPER

      Vol:
    E96-C No:4
      Page(s):
    501-510

    Modern field programmable gate arrays (FPGAs) with heterogeneous resources are partially reconfigurable. Existing methods of reconfiguration-aware floorplanning have limitations with regard to homogeneous resources; they solve only a part of the reconfigurable problem. In this paper, first, a precise model for partially reconfigurable FPGAs is formulated, and then, a two-phase floorplanning approach is presented. In the proposed approach, resource distribution is taken into consideration at all times. In the first step, a resource-aware insertion-after-remove perturbation is devised on the basis of the multi-layer sequence pair constraint graphs, and resource-aware slack-based moves (RASBM) are made to satisfy resource requirements. In the second step, a resource-aware fixed-outline floorplanner is used, and RASBM are applied to pack the reconfigurable regions on the FPGAs. Experimental results show that the proposed approach is resource- and reconfiguration-aware, and facilitates stable floorplanning. In addition, it reduces the wire-length by 4–28% in the first step, and by 12% on average in the second step compared to the wire-length in previous approaches.

  • Performance Measurement of Compact and High-Range Resolution 76 GHz Millimeter-Wave Radar System for Autonomous Unmanned Helicopters

    Shunichi FUTATSUMORI  Akiko KOHMURA  Naruto YONEMOTO  

     
    PAPER-Microwaves, Millimeter-Waves

      Vol:
    E96-C No:4
      Page(s):
    586-594

    We propose a compact and high-range resolution 76 GHz millimeter-wave radar system for autonomous unmanned helicopters. The purpose of the radar system is to detect and avoid obstacles that may affect the flight safety. To achieve these objectives, a high range resolution and a long detection range are required for the radar systems with small volume and weight. The radar broadband RF front-end module which employs a simple direct conversion method is proposed. The radar module enables the 6 GHz RF signal transmission as well as the output power of about 8 dBm using commercially available low-cost monolithic microwave integrated circuits. The radar system comprises the broadband RF front-end module, a Ku-band local frequency-modulated continuous wave signal synthesizer, and a very light weight carbon fiber reinforced plastic parabolic reflector antenna. The 5 cm of range resolution is experimentally obtained using the 6 GHz RF signal bandwidth. The results of the power line measurement confirm an about 23 dB signal to noise ratio, which is measured from the reflection of the high-voltage power lines about 150 m ahead. In addition, the results of the radar system on-board test using an unmanned helicopter are evaluated. The real-time radar scope, which is transferred through the wireless connection, confirms the detection of the power lines and the other surrounding objects.

  • A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs

    Ahmed MUSA  Kenichi OKADA  Akira MATSUZAWA  

     
    PAPER

      Vol:
    E96-C No:4
      Page(s):
    577-585

    Capacitive feedback VCOs use capacitors that are connected from the output node to the gate of the tail transistor that acts as a current source. Using such feedback results in modulating the current that is used by the oscillator and therefore changes its cyclostationary noise properties which results in a lower output phase noise. This paper presents a mathematical study of capacitive feedback VCOs in terms of stability and phase noise enhancement to confirm stability and to explain the enhancement in phase noise. The derived expression for the phase noise shows an improvement of 4.4 dB is achievable by using capacitive feedback as long as the VCO stays in the current limited region. Measurement results taken from an actual capacitive feedback VCO implemented in a 65 nm CMOS process also agrees with the analysis and simulation results which further validates the given analysis.

  • Multichannel Two-Stage Beamforming with Unconstrained Beamformer and Distortion Reduction

    Masahito TOGAMI  Yohei KAWAGUCHI  Yasunari OBUCHI  

     
    PAPER-Engineering Acoustics

      Vol:
    E96-A No:4
      Page(s):
    749-761

    This paper proposes a novel multichannel speech enhancement technique for reverberant rooms that is effective when noise sources are spatially stationary, such as a projector fan noise, an air-conditioner noise, and unwanted speech sources at the back of microphones. Speech enhancement performance of the conventional multichannel Wiener filter (MWF) degrades when the Signal-to-Noise Ratio (SNR) of the current microphone input signal changes from the noise-only period. Furthermore, the MWF structure is computationally inefficient, because the MWF updates the whole spatial beamformer periodically to track switching of the speakers (e.g. turn-taking). In contrast to the MWF, the proposed method reduces noise independently of the SNR. The proposed method has a novel two-stage structure, which reduces noise and distortion of the desired source signal in a cascade manner by using two different beamformers. The first beamformer focuses on noise reduction without any constraint on the desired source, which is insensitive to SNR variation. However, the output signal after the first beamformer is distorted. The second beamformer focuses on distortion reduction of the desired source signal. Theoretically, complete elimination of distortion is assured. Additionally, the proposed method has a computationally efficient structure optimized for spatially stationary noise reduction problems. The first beamformer is updated only when the speech enhancement system is initialized. Only the second beamformer is updated periodically to track switching of the active speaker. The experimental results indicate that the proposed method can reduce spatially stationary noise source signals effectively with less distortion of the desired source signal even in a reverberant conference room.

  • A Survey on Statistical Modeling and Machine Learning Approaches to Computer Assisted Medical Intervention: Intraoperative Anatomy Modeling and Optimization of Interventional Procedures Open Access

    Ken'ichi MOROOKA  Masahiko NAKAMOTO  Yoshinobu SATO  

     
    SURVEY PAPER-Computer Assisted Medical Intervention

      Vol:
    E96-D No:4
      Page(s):
    784-797

    This paper reviews methods for computer assisted medical intervention using statistical models and machine learning technologies, which would be particularly useful for representing prior information of anatomical shape, motion, and deformation to extrapolate intraoperative sparse data as well as surgeons' expertise and pathology to optimize interventions. Firstly, we present a review of methods for recovery of static anatomical structures by only using intraoperative data without any preoperative patient-specific information. Then, methods for recovery of intraoperative motion and deformation are reviewed by combining intraoperative sparse data with preoperative patient-specific stationary data, which is followed by a survey of articles which incorporated biomechanics. Furthermore, the articles are reviewed which addressed the used of statistical models for optimization of interventions. Finally, we conclude the survey by describing the future perspective.

  • Survey of IPX (IP eXchange) as an Emerging International Interconnection between Telecommunication Networks

    Takaaki MORIYA  

     
    SURVEY PAPER-Network

      Vol:
    E96-B No:4
      Page(s):
    927-938

    The widespread adoption of IP-based telecommunication core networks is leading to a paradigm shift in international interconnection where the traditional Time-Division Multiplexing (TDM) interconnection between telecommunication networks is being replaced by IP interconnection. IP eXchange (IPX) is an emerging paradigm in international IP interconnection that has novel requirements, such as an end-to-end Quality of Service (QoS) guarantee across multiple carriers. IPX is a future direction for international telecommunications, but it is not easy to understand the overall concept of IPX because it is derived from a wide variety of services, technical knowledge, and telecommunication backgrounds. The confusion and complexity of the technical elements hinder the development of IPX. Thus, this paper clarifies the state-of-the-art technical elements from an IPX perspective and discusses ongoing challenges and emerging services on IPX, particularly end-to-end QoS, Voice over IP issues, IP Multimedia Subsystem (IMS) interworking, and Long Term Evolution (LTE) roaming. This paper also surveys published academic research studies that were not focused primarily on IPX but which are likely to provide potential solutions to the challenges.

  • A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks

    Meng XU  Xincun JI  Jianhui WU  Meng ZHANG  

     
    PAPER-Fundamental Theories for Communications

      Vol:
    E96-B No:4
      Page(s):
    939-947

    This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

11401-11420hit(42807hit)