An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

In this paper, we present a design for an optical video transmission system employing a super wide-band FM modulation scheme. We focus on the design of optical transmitters and receivers, especially a wide-band electrical-to-optical converter and optical-to-electrical converter. With this system, it is important to develop optical and microwave devices which have a wide frequency response combined with flat group delay characteristics in order to improve the quality of the video signals after transmission. We also analyze theoretically the hybrid transmission capacity of AM analog video signals and 64QAM signals for digital video and data, and show the FM modulation parameters needed to realize high quality transmission. An experimental evaluation shows that our designed optical transmitter and receiver achieve high quality for the various channel plans for AM/64QAM hybrid transmission. The system has high received optical sensitivity and a wide optical dynamic range, allowing it to distribute analog video, digital video, and Internet data to many users over a wide area.

This paper proposes the Vector Evaluated GA-ICT (VEGA-ICT), a novel design method that employs the Genetic Algorithm (GA) to obtain the optimum antenna design. GA-ICT incorporates an arbitrary wire-grid model antenna to derive the optimum solution without any basic structure or limitation on the number of elements by merely optimizing an objective function. GA-ICT comprises the GA and an analysis method, the Improved Circuit Theory (ICT), with the following characteristics. (1) To achieve optimization of an arbitrary wire-grid model antenna without a basic antenna structure, the unknowns of the ICT are directly assigned to variables of the GA in the GA-ICT. (2) To achieve a variable number of elements, duplicate elements generated by using the same feasible region are deleted in the ICT. (3) To satisfy all complex design conditions, the GA-ICT generates an objective function using a weighting function generated based on electrical characteristics, antenna configuration, and size. (4) To overcome the difficulty of convergence caused by the nonlinearity of each term in the objective function, GA-ICT adopts a vector evaluation method. In this paper, the novel GA-ICT method is applied to downsize sector antennas. The calculation region in GA-ICT is reduced by adopting cylindrical coordinates and a periodic imaging structure. The GA-ICT achieves a 30% reduction in size compared to the previously reported small sector antenna, MS-MPYA, while retaining almost the same characteristics.

A quality-of-service based link control scheme to counteract correlated channel errors for wireless multimedia communications is proposed in this paper. Both the medium access (MAC) and data link control (DLC) layers are treated. The performance of the proposed scheme is evaluated using both analysis and simulation. The delay and jitter behaviors are examined for both the constant bit rate (CBR) traffic and variable bit rate (VBR) traffic. The throughput performance is also obtained for the available bit rate (ABR) traffic. Through numerical experiments, the proposed scheme is demonstrated to be not only robust against channel impairments but also capable of providing the desired QoS for wireless multimedia communications.

The IEEE 1394 is a standard for the high performance serial bus interface. This standard has the isochronous transfer mode that is suitable for real-time applications and the asynchronous transfer mode for delay-insensitive applications. It can be used to construct a small-size local area network. We propose a queueing model for a network with this standard under some assumptions, and calculate the average waiting time of an asynchronous packet in the buffer in the steady state. We give some numerical results, along with validation by simulation, in order to evaluate its performance.

A multi-grid finite-difference time-domain (FDTD) method was applied for numerical dosimetry analysis in the human head for 5 GHz band portable terminals. By applying fine FDTD grids to the volumes in the human head where the highest electromagnetic (EM) absorption occurs and coarse grids to the remaining volumes of the head, the spatial peak specific absorption rate (SAR) assessment was achieved with a less computation memory and time. The accuracy of applying the multi-grid FDTD method to the spatial peak SAR assessment was checked in comparison with the results obtained from the usual uniform-grid method, and then the spatial peak SARs for three typical situations of a person using a 5.2 GHz band portable terminal were calculated in conjunction with an anatomically based human head model.

In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

This paper presents the performance of the Directionally Constrained Minimization of Power (DCMP) and the Zero-Forcing (ZF) in the Angular Spread (AS) environment. To obtain the optimal weights for both methods, the Extended Array Mode Vector (EAMV) is employed. It is known that the EAMV represents the instantaneous AS as well as the instantaneous DOA in the slow fading channel. As a result, it is shown that the DCMP and the ZF using the EAMV estimates can improve the Signal-to-Interference-plus-Noise Ratio (SINR) considerably, as compared with those using the Direction of Arrival (DOA) information only. At the same time, the intrinsic problems causing the performance loss in the DCMP and the ZF are revisited. From this, the reasons for the performance deterioration are analyzed, in relation with the AS, the number of samples, the number of antenna elements, and the spatial correlation coefficient of the signals. It follows that the optimal signal combining techniques using the EAMV estimates can diminish such effects.

We present a simple cell scheduling algorithm for an input buffered switch. The suggested algorithm is based on iSLIP and consists of request, grant and accept steps. The pointer update scheme of iSLIP is simplified in the suggested algorithm. By virtue of the new update scheme, the performance of the suggested algorithm is better than that of iSLIP with one iteration. Using computer simulations under a uniform traffic, we show the suggested algorithm is more appropriate than iSLIP for scheduling of an input buffered switch with multiple service classes.

In this letter, we propose a grammatical structure of the finite state network (FSN) for the recognition of Korean price sentences. It is implemented by arranging the nodes and the arcs of the FSN. Two kinds of grammatical structure are presented. Both are designed according to the grammar constraints of Korean price sentences. The grammar constraints of Korean price sentences are similar to those of English price sentences; the unit is placed after the digit; several digits form a basic group; the basic group appears recursively followed by meta-units, etc. Speaker-independent recognition experiments were conducted, and the results of the FSN's with proposed grammatical structures were compared with those of the FSN without grammatical structure.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

In this paper, we present a new signal frequency estimation method based on the sinusoidal additive synthesis model. In the proposed method, frequencies in both the signal and noise are estimated with several delay times by using an expanded linear prediction (LP) method, and assuming that the signal is stationary and noise is unstationary in short record length. Frequencies in the signal are extracted according to their dependence on different delays. The frequency estimation can be accomplished with short record length even in the case where the number of frequency components in the signal is unknown. And it is capable of estimating the frequencies of a signal in the presence of noise. Furthermore, the proposed method estimates the parameters with less computation and high estimation accuracy. Simulation results are provided to confirm the effectiveness of the proposed method. The comparison of estimation accuracy between the proposed method and the analysis by synthesis (ABS) method is shown with the corresponding Cramer-Rao lower bound. And the frequency resolution of this method is also shown.

Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.