The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

Heavy-ion-induced soft errors (single event upset) in submicron silicon-on-insulator (SOI) MOSFETs under space environmental conditions are studied over the temperature range of 100-400 K using three-dimensional device simulator with full-temperature models. The temperature dependence of the drain collected charge is examined in detail when a heavy-ion strikes the gate center perpendicularly. At very low temperatures, SOI MOSFETs have very high immunity to the heavy-ion-induced soft errors. In particular, alpha-particle-induced soft errors hardly occur at temperatures below 200 K. As the temperature increases, the collected charge shows a marked rate of increase. The problem of single event upset in SOI MOSFETs becomes more serious with increasing working temperature. This is because the induced bipolar mechanism is a main factor to cause charge collection in SOI MOSFETs and the bipolar current increases exponentially with increasing temperature. At room and high temperatures, the drain collected charge is strongly dependent on channel length and SOI film thickness.

In the proposed architecture, switching system hardware resources are allocated at the equipment level rather than at the component level of LSI chips. Equipment using these resources can thus be shared between independent systems. The efficiency of system development is improved by using structural elements called functional blocks (FBs). The hardware in each FB consists of a shared part (amicroprocessor, its peripheral circuitry, and memory) and a dedicated part that implements the specific functions of the FB. Firmware loaded into the microprocessor consists of a shared part and a dedicated part that corresponds to the hardware parts. Each FB also has its own built-in autonomous testing function to test the reliability of that FB and has its own identification function. By combining these FBs, this approach can flexibly cope with various switching system configurations for plain old telephone service (POTS), integrated services digital network (ISDN), and broad-band ISDN (B-ISDN). Tests using several types of FBs showed that the shared hardware and firmware parts of an FB can be shared between blocks. An architecture based on FBs results in a platform that can handle the hardware for various systems, making it easy to construct new switching systems.

The asynchronous transfer mode (ATM) provides efficient switching capability for various kinds of communication services. To guarantee the minimum quality of services in the ATM networks, the bandwidth allocation setup procedure between the network nodes and users is very important. However, most of call admission control (CAC) methods which have been proposed so far are not fully appropriate to apply to real environments in terms of the complexity of the hardware implementation or the accuracy of assumptions about the cell-arrival processes. In addition, the success of broad bandwidth applications in the future multimedia environments will largely depend on the degree to which the efficiency in communication systems can be achieved, so that establishing high-speed CAC schemes in the ATM networks is an indispensable subject. This paper proposes a new cell-loss rate estimation method for the real time CAC in ATM networks. A neural network model using the Kalman filter algorithm was employed to improve the error minimizing process for the cell-loss estimation problem. In the process of optimizing the three-layer perceptron, the average, the variance, and the 3rd central moment of the number of cell arrivals were calculated, and cell-loss rate date based on the non-parametric method were adopted for outputs of the neural network. Evaluation results concerned with the convergence using the sum of square errors of outputs were also discussed in this paper. Using this algorithm, ATM cell-loss rates can be easily derived from the average and peak of cells rates coming from users. Results for the cell-loss estimation process suggest that the proposed method will be useful for high-speed ATM CAC in multimedia traffic environments.

This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.

This paper presents severl radio resource scheduling algorithms which aim to provide best-effort service for non-real-time unit-oriented, or message traffic. The objective of resource scheduling algorithm is to distribute radio resources between competing message traffic sources while attaining throughput as high and fair as possible for each source without any explicit quality-of-service (QoS) guarantee. Computer simulations are carried out to evaluate the performance in terms of the average of allocation plus transfer delay, the average of throughput, the variance of throughput, and the usage of resources. The message-size distributions of homepages in World-Wide-Web and e-mails obtained by actual measurement are used. Message size-based resource scheduling algorithms are found to provide high and fair throughput as well as efficient use of the resources.

In this paper, algorithms for resource allocation in an ATM node that serves heterogeneous traffic sources subject to varying Quality of Service (QoS) requirements are proposed. The node can be either a switch port or a multiplexer. Each connection is first individually treated as logical queue. Quick and efficient algorithms allocating service rate and buffer space to each connection based on traffic characteristics and QoS requirement are developed. In order to improve link and buffer utilization, the aggregate traffic is next replaced by an appropriately parameterized new traffic source that still preserves the key characteristics of the aggregate traffic. The most stringest QoS requirement among all connections is selected to be the QoS target of the new traffic source to assure that QoS of each individual connection is satisfied. Resource allocation for the aggregate traffic is determined based on the traffic parameters and QoS target of the new source. Each individually determined service rate and buffer space can be used in cell transmission scheduling and selective cell discarding. In other words, resource allocation together with two related side problems: cell transmission and cell discarding, are treated in this paper in an integrated and efficient manner. The resource allocation algorithms proposed in this paper can also be used to support Call Admission Control (CAC) in ATM networks.

For L 2, M 8, and transmission rate R = (log2M-1) bit/sym, a method for constructing GU trellis codes with L MPSK constellations is proposed and it is shown that the maximally achievable free distance is twice larger than it was previously reported for GU codes. Basides being geometrically uniform, these codes perform as good as Pietrobon's non-GU trellis codes with multidimensional MPSK constellations.

In this paper we present an algorithm to solve an as-yet untreated knapsack problem, the Multidimensional Multiple-choice Knapsack Problem (MMKP). Since our specific application occurs in the real-time domain, a solution for the MMKP with a small upper bound on the runtime is desirable. Thus, the Lagrange multiplier method is chosen, and a heuristic with a worst-case runtime behavior better than O(n2m) is developed, n being the number of elements and m the number of dimensions. Extensive testing against an exact algorithm based on partial enumeration is used to establish the accuracy and efficiency of the heuristic.

Genetic algorithms have been shown to be very useful in a variety of search and optimization problems. In this paper we present a genetic algorithm for maximum independent set problem. We adopt a permutation encoding with a greedy decoding to solve the problem. The DIMACS benchmark graphs are used to test our algorithm. For most graphs solutions found by our algorithm are optimal, and there are also a few exceptions that solutions found by the algorithm are almost as large as maximum clique sizes. We also compare our algorithm with a hybrid genetic algorithm, called GMCA, and one of the best existing maximum clique algorithms, called CBH. The exiperimental results show that our algorithm outperformed two of the best approaches by GMCA and CBH in final solutions.

In this paper, a block implementation of high-speed IIR adaptive noise canceller is proposed. First, the block difference equation of an IIR filter is derived by the difference equation for high-speed signal processing. It is shown that the computational complexity for updating the coefficients of IIR adaptive filter can be reduced by using the relations between the elements of coefficient matrices of block difference equation. Secondly, the block implementation of IIR adaptive noise canceller is proposed in which the convergence rate is increased by successively adjusting filter Q-factors. Finally, the usefulness of proposed block implementation is verified by the computer simulations.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

This paper reports on the design and performance of a very fast Track/Hold (T/H) circuit with GaAs Heterojunction Bipolar Transistor (HBT) to precede a 3GS/s 6 bit ADC. The T/H circuit employs a differential open-loop architecture for high-speed operation, and it consists of diode bridge switches, hold capacitors and output buffers. The differential structure as well as the output buffers suppress droop effects due to the small hFE (20) of our HBT. Measured results show that the T/H circuit has better than 6 bit linearity within an input range of 1.0 Vp-p with power dissipation of 990m W, and the bandwidth is 6 GHz in the track mode. The measured droop rate is 2.1mV/ns, the feedthrough is -46 dB 500 MHz and the hold pedestal is less than 10m V. Also a 3 GHz sampling operation of the T/H circuit was measured. The T/H circuit uses 43 HBTs, 24 Schottky barrier diodes and occupies a chip area of 1.4 1.75 mm2. We also describe the design and performance of a variable, gain amplifier with GaAs HBT to precede the T/H circuit as an input buffer and adjust its gain. These results support the possibility of meeting the requirements for a high-speed ADC system.

This paper presents an efficient optimal block terminal assignment algorithm based on the integer programming for a data path synthesis. The problem is to assign buses to commutable terminals on functional units such that the number of buses is minimum, when the scheduling and allocation of operations and registers have been done. Three methods are used in the algorithm to decrease the amount of computation.

Geometrically Uniform (GU) codes have been a center of attention because their symmetric properties along with group algebraic structure provide benefits on their design and perfomance evaluation. We have been following a class of GU codes tha we call Strictly Geometrically Uniform (SGU) codes. Our studies had started from devising a way to get SGU trellis codes from Non-SGU (NSGU) constellations. Essentially, SGU multidimensional constellations were derived from an 1- or 2-dimensional NSGU constellations. Some simple good codes were then found, and the novelty is that they rely on symmetries of permutation of channel symbols. Applying the same method to PSK-type constellations, which is SGU, yielded again good codes, along with results regarding their algebraic structure.

A leaky-bucket-with-gate algorithm is proposed to control connection-setup congestion in telecommunication networks providing multimedia services, in place of the call-gapping algorithm used in telephone networks. Multimedia services may use more than one connection simultaneously, while standard telephone services use only one connection at a time. A set of connections used to construct a multimedia service is called a correlated connection group, and the setup requests of such a group form correlated request group. A correlated request group is assumed to be accepted into the network only when all the connection-setup requests for the group are accepted. In this paper, the proposed leaky-bucket-with-gate algorithm, a pure leaky-bucket algorithm, and a call-gapping algorithm are evaluated by simulating traffic with a mix of correlated and uncorrelated connection-setup requests, which models setup requests for video conferencing and telephone services. The simulation results show that the proposed algorithm accepts correlated request groups more efficiently than the pure leaky-bucket and call-gapping algorithms under the simulated traffic conditions, except when the interarrival time in a correlated request group is longer than the acceptance interval. We also present queueing analysis for determining the control parameters in the proposed algorithm. Implementation of this algorithm will facilitate the handling of both setup request traffic for correlated connection groups and for uncorrelated connections in multimedia networks.

In the conventional sound field reproduction system with control of the transfer functions from the source to both ears of a listener, a slight shift of the ears caused by movement of the listener inevitably results in sound localization being different from that expected. In this paper, a method for reproducing a sound field by controlling the transfer function from the source to multiple points (called the "method of multiple-points control" hereafter) is applied to a sound reproduction system with the aim of expanding the area which can be controlled. The system is controlled so that the transfer functions from the input of the system to the multiple points adjacent to the original receiving points have the same desired transfer function. By placing the control points at appropriate intervals, a "zone of equalization" is formed. Based on a computer simulation, the intervals between control points is discussed. The configuration of the loundspeakers for sound reproduction is also discussed.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

This paper describes what happens when the silicon layer is extremely thinned. The discussion shows that quantum mechanical short-channel effects impose limits on the down-scaling of MOSFET/SOI devices. However, thinning the silicon layer should bring new possibilities such as mobility enhancement, velocity overshoot enhancement, suppression of band-to-band tunneling, suppression of impact ionization and so on. Furthermore, the non-stationary energy transport in extremely miniaturized ultra-thin MOSFET/SOI devices is also addressed from the viewpoint of hot-carrier immunity. Related device physics are also discussed in order to consider the design methodology for contemporary MOSFET/SOI devices and new device applications for the future.