In the adaptive lattice estimation process, it is well known that the convergence speed of the successive stage is affected by the estimation errors of reflection coefficients in its preceding stages. In this paper, we propose block estimation methods of two-dimensional (2-D) adaptive lattice filter. The convergence speed of the proposed algorithm is significantly enhanced by improving the adaptive performance of preceding stages. Furthermore, this process can be simply realized. The modeling of 2-D AR field and texture image are demonstrated through computer simulations.

Analog inverter is one of the most useful building blocks in analog circuits. This paper proposes an analog inverter consisting of a p-channel MOS (PMOS) and an n-channel MOS (NMOS) inverter and presents an application to all-pass filter realizations. The proposed circuit has a wide dynamic range by combining PMOS and NMOS inverters. When the proposed analog inverter is applied to an all-pass filter, the circuit configuration becomes simpler and occupies less chip area and power consumption.

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.

A factorization method for a string polynomial called the constant method is proposed. This uses essentially three operations; classification of monomials, gcrd (greatest common right divisor), and lcrm (least common rigth multiple). This method can be applied to string polynomials except that their constants cannot be reduced to zeros by the linear transformation of variables. To factorize such excluded string polynomials, the naive method is also presented, which computes simply coefficients of two factors of a given polynomial, but is not efficient.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

A novel technique is proposed to fabricate a chirped fiber Bragg grating utilizing thermal diffusion of core dopant. The chirped grating is written with a uniform period by using UV exposure technique in the fiber whose effective index of the guided mode varies along its length. Thermal diffusion of the core dopant it employed to realize this change of the effective index. Through the thermal diffusion process, the effective index of the fiber decreases from its initial value. When the grating is written in the diffused core region, its reflection wavelength becomes shorter than that in the non-diffused region. The continuous change of effective index is required for making a chirped grating. The fiber is heated by a non-uniform heat source. When the uniform grating is written in this region, the reflection wavelength smoothly changes along the fiber length although the grating period is constant. By optimizing the fiber parameters to realize a highly chirped grating, we have obtained a typical one whose bandwidth is 14.1 nm at half maximum and maximum rejection in transmission is 29 dB. Additionally, the proposed method has an advantage to control the chirp profile with high mechanical reliability.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

In this paper, we consider the following node-to-set disjoint paths problem: given a node s and a set T = {t1,...,tk} of k nodes in a k-connected graph G, find k node-disjoint paths s ti, 1 i k. We give an O(n2) time algorithm for the node-to-set disjoint paths problem in n-dimensional star graphs Gn which are (n - 1)-connected. The algorithm finds the n - 1 node-disjoint paths of length at most d(Gn) + 1 for n 4,6 and at most d(Gn) + 2 for n = 4,6, where d(Gn) = 3(n-1)/2 is the diameter of Gn. d(Gn) + 1 and d(Gn) + 2 are also the lower bounds on the length of the paths for the above problem in Gn for n 4,6 and n = 4,6, respectively.

A new numerical technique, termed the method of matrix-order reduction (MMOR), is developed for handling electromagnetic problems in this paper, in which the matrix equation resulted from a method-of-moments analysis is converted either to an eigenvalue equation or to another matrix equation with the matrix order in both cases being much reduced, and also, the accuracy of solution obtained by solving either of above equations is improved by means of a newly proposed generalized Jacobian iteration. As a result, this technique enjoys the advantages of less computational expenses and a relatively good solution accuracy as well. To testify this new technique, a number of wire antennas are examined and the calculated results are compared with those obtained by using the method of moments.

We apply a novel methodology, based on statecharts, to the design of large scale asynchronous systems. The design is specified at multiple levels, simulated, animated, and compiled into synthesizable VHDL code by using the ExpressV-HDL CAD tool. We add a validation sub-system to chech correct operation. ExpressV-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependence on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronous circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

In the conventional sound field reproduction system with control of the transfer functions from the source to both ears of a listener, a slight shift of the ears caused by movement of the listener inevitably results in sound localization being different from that expected. In this paper, a method for reproducing a sound field by controlling the transfer function from the source to multiple points (called the "method of multiple-points control" hereafter) is applied to a sound reproduction system with the aim of expanding the area which can be controlled. The system is controlled so that the transfer functions from the input of the system to the multiple points adjacent to the original receiving points have the same desired transfer function. By placing the control points at appropriate intervals, a "zone of equalization" is formed. Based on a computer simulation, the intervals between control points is discussed. The configuration of the loundspeakers for sound reproduction is also discussed.

This paper reviews the structure and electrical properties of high-quality Internal Thermal OXidation (ITOX)-processed low-dose Separation by IMplanted OXygen (SIMOX) wafers. The ITOX SIMOX process consists of three steps: low-dose oxygen implantation, high-temperature annealing, and high-temperature oxidation. The low dose makes possible a high-throughput production of SIMOX wafers. The high-temperature annealing provides a continuous buried oxide layer and reduces the dislocation density in the top silicon layer. The subsequent high-temperature oxidation thickens the buried oxide layer without any additional oxygen implantation, thus improving its electrical properties. The ITOX mechanism is also described. It is concluded that the ITOX SIMOX wafers are very useful for fabricating ULSIs.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

The concept of a basis matrix is introduced to investigate the trade-off between complexity and storage for multiplication in a finite field. The effect on the storage requirements of using polynomial and normal bases for element representation is also considered.