A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

A novel learning algorithm for a neural network LSI which has low resolution synapse weights is proposed. Following a brief discussion of the synapse weight adaptation mechanism in the gradient descent scheme, we propose a way of achieving relaxation from the influence of discretized weight. Restriction of the number of synapses to be updated in one learning iteration is effective to relax the influence. Simulation results support the effectiveness of this learning algorithm. Low resolution synapses will be practical to realize large-scale neural network LSIs.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

In client-server database management systems (DBMSs), inter-transaction caching is an effective technique for improving the performance. However, inter-transaction caching requires a cache consistency maintenance (CCM) protocol to ensure that cached copies at clients are kept mutually consistent. Such a protocol could be complex to implement and expensive to run, since several rounds of message exchange may be required. In this paper, we propose a new CCM scheme based on the primary-copy locking algorithm. In the proposed scheme, a number of lock requests and a data-shipping request are combined into a single message packet to reduce client-server interactions, which are known to be very critical to the performance of clientserver DBMSs. We examine its performance tradeoffs on the basis of a simulation model under a wide range of workloads. The performance results indicate that the proposed scheme improves the overall system throughput significantly over the caching two-phase locking and the optimistic two-phase locking scheme. Its higher performance mainly results from its lower communication overhead and lower degree of transaction blocking ratio.

Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

This paper describes research on a cost-effective regional Personal-Computer (PC) communication network system based on Fiber-to-the-Home (FTTH) systems and examines its realization. A small scale prototype experimental system was developed and tested in a home-use trial. This paper specifically discusses a sophisticated system architecture with a newly developed miutiplex-port brouter (bridging router) based on the experimental system. The system provides a LAN environment and group communication services to the customers. The Low-end Card (LEC), which provides the popular Ethernet interface (10Base-T), is set up in the subscriber household. The leased circuits are connected between the LEC and the brouter. The LEC and the brouter are controlled by the management server to function as a group communication system. The brouter, which has a multiplex subscriber-port interface, must accommodate many customers in a cost effective manner. This paper presents the system design of a multiplex-port brouter with an SDH/SONET interface. Two types of interface cards at 150 Mbit/s and 50 Mbit/s are prepared making the system scalable. The brouter can accommodate up to 2,700 subscribers. The subscriber channel rate can be set from 64 Kbit/s to 1.5 Mbit/s. Ethernet packets from the PCs are transferred through each subscriber channel between the LEC and the brouter using the High-level Data Link Control (HDLC) protocol.

We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

A new configuration of high gain circularly polarized microstrip antenna with a diagonal short and its analysis using boundary element method with a radiation load are presented. The center of a radiating patch is shorted with a 45-degree diagonal offset for not only obtaining a high gain but exciting a circular polarization. This configuration leads to achieving high gain with keeping a very low profile configuration. Boundary element method with radiation load which takes into account the effect of radiation loss is employed to analyze this complicated configuration. The radiation load, which is very important when boundary element method is applied to antenna analyses, can be obtained from radiation admittance using recurring technique, so that the accuracy of the antenna characteristic calculations can be improved. This antenna was designed and tested in the L-band and good characteristics, axial ratios and radiation patterns, have been verified.

A new method is proposed for estimating a single complex sinusoid and its parameters (frequency and amplitude) from measurements corrupted by white noise. This method is called the ECKF-SVD method, which is derived by applying an extended complex Kalman filter (ECKF) to a nonlinear stochastic system whose state variables consist of the AR coefficient (a function of frequency) and a sample of the original signal. Proof of the stability is given in the case of a single sinusoid. Simulations demonstrate that the proposed ECKF-SVD method is effective for estimating a single complex sinusoid and its frequency under a low signal-to-noise ratio (SNR). In addition, the amplitude estimation by means of the ECKF-SVD method is also discussed.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

We propose a memory-based processor called a Functional Memory Type Parallel Processor for vector quantization (FMPP-VQ). The FMPP-VQ is intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search on vector quantization. In the nearest neighbor search, we look for a vector nearest to an input one among a large number of code vectors. The FMPP-VQ has as many PEs (processing elements, also called "blocks") as code vectors. Thus distances between an input vector and code vectors are computed simultaneously in every PE. The minimum value of all the distances is searched in parallel, as in conventional CAMs. The computation time does not depend on the number of code vectors. In this paper, we explain the detail of the architecture of the FMPP-VQ, its performance and its layout density. We designed and fabricated an LSI including four PEs. The test results and performance estimation of the LSI are also reported.

Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

The TLS method is an unbiased estimator for solving the overdetermined set of linear equations when errors occur in all data. However it doesn't show robustness while the errors have a heavy tailed pdf. In this letter we derive a robust method of TLS (ROTLS) based on the characteristics of TLS solution, where the performance of ROTLS is verified by applying it to the system identification problem.

A sparse memory access architecture which is proposed to achieve a high-computational-speed neural-network LSI is described in detail. This architecture uses two key techniques, compressible synapse-weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without incurring an accuracy penalty. The test chip based on this architecture has 96 parallel data-driven processing units and enough memory for 12,288 synapse weights. In a pattern recognition example, the number of memory accesses and neuron calculations was reduced to 0.87% that needed in the conventional method and the practical performance was 18 GCPS. The sparse memory access architecture is also effective when the synapse weights are stored in off-chip memory.

The paper provides the algorithm to estimate the deviation bound admitting to recovering irregularly sampled signals in wavelet subspaces, which does not need the symmetricity sampling constraint of Paley-Wiener's and relaxes the deviation bounds in some wavelet subspaces. Meanwhile the method does not need the continuity and decay constraints imposed on scaling functions by Liu-Walter and Chen-Itoh-Shiki.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.