This paper describes the characteristics of a one dimensional narrow-wall slotted waveguide array with a single-layer linear-to-circular polarization converter consisting of a dipole array. An external boundary value problem of one slot and three dipoles, which approximates the mutual coupling between the dipole array and an edge slot extending over three faces of a rectangular waveguide, is formulated and analyzed by the method of moments; design of polarization conversion is conducted for this model as a unit element. If every unit element has perfect circular polarization, grating lobes appear in the array pattern due to the alternating slot angle: these are suppressed in this paper by changing the dipole angle and degrading the axial ratio of the unit element. The validity of the design is confirmed by the measurements. The dipole array has negligible effects upon slot impedance; the polarization conversion for existing narrow-wall slotted arrays is realized by add-on dipole array.

High-speed display of 3-D objects in virtual reality environments is one of the currently important subjects. Shape simplification is considered an efficient method. This paper presents a method of hierarchical cube-based segmentation for shape simplification and multiresolution model construction. The relations among shape simplification, resolution and visual distance are derived firstly. The first level model is generated from scattered range data by cube-base segmentation with the first level cube size. Multiresolution models are then generated by re-sampling polygonal patch vertices of each former level model with hierarchical cube-based segmentation structure. The results show that the algorithm is efficient for constructing multiresolution models of free-form shape 3-D objects from scattered range data and high compression ratio can be obtained with little noticeable difference during the visualization.

This paper discusses a design method for two-dimensional (2-D) periodically time-variant digital filters (PTVDFs) whose filter coefficients vary periodically. First, 2-D periodicities for a variation of filter cefficients are considered, from which two and four-phase variations of coefficients are shown to be suitable for practical applications. Then, the input-output relation (transfer function) for 2-D separable-denominator (SD) PTV DFs is derived, which results in a linear combination of the baseband input signal and its modulated versions. Finally, in order ro approximate given filter specifications, the structure for 2-D SD PTV DFs is given and a design method is proposed. It is shown that, compared with the 2-D SD time-invariant DFs, approximation error can be reduced with the proposed SD PTV DFs.

This paper proposes a novel FEC (forward error correction) scheme for high-speed wireless systems aiming at mobile computing applications. The proposed scheme combines inner nonredundant error correction with outer parallel encoding random FEC for differentially detected QPSK (quadrature phase shift keying) signals. This paper, first, examines error patterns after the differential detection with nonredundant error correction and reveals that particular double symbol errors occur with relatively high probability. To improve the outer FEC performance degradation due to the double symbol errors, the proposed scheme uses I and Q channel serial to parallel conversion in the transmission side and parallel to serial conversion in the receiving side. As a result, it enables to use simple FEC for the outer parallel encoding random FEC without interleaving. Computer simulation results show the proposed scheme employing one bit correction BCH coding obtains a required Eb/No improvement of 1.2 dB at a Pe of 10-5 compared to that with the same memory size interleaving in an AWGN environment. Moreover, in a Rician fading environment where directional beam antennas are assumed to be used to improve the degradation due to severe multipath signals, an overall Eb/No improvement at Pe of 10-5 of 3.0 dB is achieved compared to simple differential detection when the condition of delay spread of 5 nsec, carrier to multipath signal power ratio of 20 dB and Doppler frequency at 20 GHz band of 150 Hz.

Based on a recent remarkable development of digital beamforming (DBF) antenna technologies, we propose a new concept of kaleidoscopic antenna, we call it "software antenna," which is a more general one extending DBF schemes. The software antenna instantly reconfigures itself adapting its software and hardware to changes in the radio-environment. To realize the software antenna, the development of high-speed reconfigurable FPGAs is indispensable. As an intelligent antenna, we believe the software antenna could play a key role in the days of software radio having a function of mobile computing.

In this paper,a protocol-based modeling and simulation method of performance evaluation for heavy traffic and transient LAN is proposed. In the method a node on a LAN is modeled as a set of detailed communication protocol models. By parallel and event driven processing of the models, high accuracy and high time-resolution of evaluation of LAN behaviors can be obtained at multi-layer protocols. The LANs at computer education sites have highly loaded peaks, and it is very hard to design large scale educational LANs. Proposed method can be used to evaluate such cases of heavy traffic and transient LAN.

The finite reconfigurability and local reconfigurability of graphs were proposed by Sha and Steiglitz [1], [2] in connection with a problem of on-line reconfiguraion of WSI networks for run-time faults. It is shown in [2] that a t-locally-reconfigurable graph for a 2-dimensional N-vertex array AN can be constructed from AN by adding O(N) vertices and edges. We show that Ω(N) vertices must be added to an N-vertex graph GN in order to construct a t-locally-reconfigurable graph for GN, which means that the number of added vertices for the above mentioned t-locally-reconfigurable graph for AN is optimal to within a constant factor. We also show that a t-finitely-reconfigurable graph for an N-vertex graph GN can be constructed from GN by adding t vertices and tN + t (t+1)/2 edges.

This paper describes a new multiple DmB1C (Differential m Binary 1 Complement insertion) /DmB1M (Differential m Binary with 1 Mark insertion) coding scheme for high-speed optical multiplex transmission. The coding scheme has the characteristics of small consecutive identical digits and a good balance between marks and spaces. Furthermore, it has also good synchronization characteristics and higher flexibility for extension to high capacity transmission than the conventional mB1C or DmB1M coding schemes. We describe a design methodology for a multiplex transmission system using the proposed coding scheme, and verify the characteristics of the proposed coding scheme using an experimental setup of a 2.8 Gbit/s serial optical interconnection circuit, which has 16 parallel 156 Mbit/s inputs. The coding scheme realizes transmission systems with simple analog circuit configuration, and small digital circuit complexity with wide dynamic range and good mark ratio tolerance.

Given the tremendous growth in the cellular phone system and the Personal Hadny-phone System (PHS), it is to be expected that demands for mobile computing using those wireless infrastructures, that is mobile computer access, will dramatically increase. This paper describes high-quality and high-speed data transmission technology for PHS mobile computing and current PHS data transmission standardization activities. Furthermore, wireless agent communication and a service example are presented together with the concept of background communication for the coming wireless multimedia services.

Recently, the number of users utilizing mobile communication services has increased greatly in many information and communication fields. In the future, the number of mobile communication system users will increase even faster, until the rate of diffusion ultimately reaches that of telephones. The day that each person has his own portable mobile terminal is not so far off. Moreover, the systems will not only be used as telephones but also as mobile computing for multimedia information. Digitalization technologies of mobile communication systems needed to realize such mobile computing will be introduced in this paper.

In this letter, the absolute exponential stability result of neural networks with asymmetric connection matrices is obtained, which generalizes the existing one about absolute stability of neural networks, by a new proof approach. It is demonstrated that the network time constant is inversely proportional to the global exponential convergence rate of the network trajectories to the unique equilibrium. A numerical simulation example is also given to illustrate the obtained analysis results.

We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

We propose a soft decision Viterbi decoding scheme and a self-interference cancellation method applicable to a Parallel Combinatory CDMA (PC-CDMA) system. In this decoding scheme, branch metric is calculated for every bit by weighting the output levels of the PC-CDMA correlators so as to enable an effective soft decision capability to the system. The effectivity of this scheme is then further enhanced by the use of a simple pseudo-random bit interleaving scheme. Moreover, to increase the capacity of the PC-CDMA system, we propose a simple self-interference cancellation method for self-induced cross-correlation arising from the multipath environment. This further enhances the efficacy of the decoding scheme because the false contributions of the self-induced cross-correlation component are removed from the branch metric prior to soft decision Viterbi decoding. Finally, we simulated a possible PC-CDMA system with a user data rate of 1.92Mbps, transmitting it at a chip rate of 3.84Mcps and at 7.68Mcps under a multipath-Rayleigh fading interference environment. For a chip rate of 7.68Mcps, BER after Viterbi decoding is less than 3.2e-7 even without the use of interference cancellation. For a chip rate of 3.84Mcps, BER after Viterbi decoding with interference cancellation is 1.0e-4.

Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

Spectral transform methods have been widely studied for classification and analysis of logic functions. Spectral methods have also been used for logic synthesis, and by use of BDDs, practical-sized synthesis problems have been solved. Wavelet theory has recently attracted the attention of researchers in the signal processing field. The Haar function is used in both spectral methods and in signal processing to obtain spectral coefficients of logic functions of signals. In this paper spectral transform-based analysis of neural nets verifying signal processing and discrete function is presented. A neural net element is defined as a discrete function with multi-valued input signals and multi-valued or binary outputs. The multi-valued variable is realized as a variable (V, W) formed by a pair of a binary value and a multi-value pulse width. The multi-valued encoding is used with the multi-valued Haar function to give meanings to the wavelet coefficients from the view of Boolean algebra. A design example shows that these conceptually different concepts are closely related.