A detailed investigation of the electromagnetic field distributions inside waveguide circuits is useful for physical understanding, studies of electromagnetic coupling effects for EMC and EMI and for optimization of waveguide circuit designs. In this paper, we describe how to calculate and measure the two-dimensional electromagnetic field distributions inside waveguide-type planar circuits, making use of an analogy between H-plane waveguide- and trough-type surface-wave planar circuits. The measurement results are in good agreement with the results of the numerical analysis based on the normal mode expansion method.

Recently, a wavelength division multi/demultiplexing system has been viewed with keen interest because it is possible to increase the transmission capacity and system flexibility. An arrayed waveguide grating (AWG) type of Multi/demultiplexer which is one of the key components to realize such a system has been developed by using Planar Lightwave Circuits (PLCs). Newly designed optical circuits have been incorporated into the AWG to control the center wavelength and to expand the pass band width. The 3 dB pass band width is 1.4 times that of a conventional AWG. It is confirmed that the newly developed AWG has low polarization dependence, low temperature dependence and high reliability.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

A new linearization technique of a transconductor is presented. The linearization is realized by using a differential current amplifier with an emitter-coupled pair. A specific value of the linearization parameter gives a maximally flat or an equiripple characteristic. Deviations from the theoretical characteristic can be adjusted by tuning the tail current of the emitter-coupled pair. The proposed technique is demonstrated by PSPICE simulation.

Wavelength Division Multiplexing (WDM) technology provides many options to the design of flexible alloptical networks. To exploit these options to their full potential, Photonic Integrated Circuits (PICs) for wavelength routing and switching will be indispensable. One of the basic building blocks of such PICs is the planar phased-array (PHASAR) wavelength demultiplexer. The monolithic integration of PHASARs with photodetectors, amplifiers, and other waveguide-based (passive) components is discussed.

Photonic integrated circuits (PICs) are required for future optical communication systems, because various optical components need to be compactly integrated in one-chip configurations with a small number of optical alignment points. Bandgap energy controlled selective metal organic vapor phase epitaxy (MOVPE) is a breakthrough technique for the fabrication of PICs because this technique enables the simultaneous formation of waveguides for various optical components in one-step growth. Directly formed waveguides on a mask-patterned substrate can be obtained without using conventional mesa-etching of the semiconductor layers. The waveguide width is precisely controlled by the mask pattern. Therefore, high device uniformity and yield are expected. Since we proposed and demonstrated this technique in 1991, various PICs have been reported. Using electroabsorption modulator integrated distributed feedback laser diodes, 2.5 Gb/s-550 km transmission experiments have been successfully conducted. Another advantage of the selective MOVPE technique is the capability to form narrow waveguide layers. We have demonstrated a polarization-insensitive semiconductor optical amplifier that consists of a selectively formed narrow (less than 1 µm wide) bulk active layer. For a four-channel array, a chip gain of more than 20 dB and a gain difference between TE and TM inputs of less than 1 dB were obtained. We have also reported an optical switch matrix and an optical transceiver PIC for access optical networks. By using a low-loss optical waveguide, a 0 dB fiber-to-fiber gain for the 14 switch matrix and 0 dBm fiber output power from the 1.3 µm transceiver PIC were obtained. In this paper, the selective MOVPE technique and its applications to various kinds of PICs are discussed.

A method of planar curve classification, which is invariant to rotation, scaling and translation using the zerocrossings representation of wavelet transform was introduced. The description of the object is represented by taking a ratio between its two adjacent boundary points so it is invariant to object rotation, translation and size. Transforming this signal to zero-crossings representation using wavelet transform, the minimum distance between the object and model while shifting the signals each other, can be used as classification parameter.

We present a general framework with which we can evaluate the flexibility and efficiency of various replay systems for parallel programs. In our approach, program monitoring is modeled by making a virtual dataflow program graph, referred to as a VDG, that includes all the instructions executed by the program. The behavior of the program replay is modeled on the parallel interpretation of a VDG based on two basic parallel execution models for dataflow program graphs: a data-driven model and a demand-driven model. Previous attempts to replay parallel programs, known as Instant Replay and P-Sequence, are also modeled as variations of the data-driven replay, i.e. the datadriven interpretation of a VDG. We show that the demand-driven replay, i.e. the demand-driven interpretation of a VDG, is more flexible in program replay than the data-driven replay since it allows better control of parallelism and a more selective replay. We also show that we can implement a demand-driven replay that requires almost the same amount of data to be saved during program monitoring as does the data-driven replay, and which eliminates any centralized bottleneck during program monitoring by optimizing the demand propagation and using an effective data structure.

We describe our implementation of the Hypercube variation of the Multiple Polynomial Quadratic Sieve (HMPQS) integer factorization algorithm on a Parsytec GC computer with 128 processors. HMPQS is a variation on the Quadratic Sieve (QS) algorithm which inspects many quadratic polynomials looking for quadratic residues with small prime factors. The polynomials are organized as the nodes of an n-dimensional cube. We report on the performance of our implementations on factoring several large numbers for the Cunningham Project.

Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

The currying of term rewriting systems (TRSs) is a transformation of TRSs from a functional form to an applicative form. We have already introduced an order-sorted version of currying and proved that the compatibility and confluence of order-sorted TRSs were preserved by currying. In this paper, we focus on a key property of TRSs, completeness. We first show some proofs omitted in Ref. [3]. Then, we prove that the SN (strongly normalizing) property, which corresponds to termination of a program, is preserved by currying. Finally, we prove that the completeness of compatible order-sorted TRSs is preserved by currying.

The advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart-Cut(R) SOI process used for the manufacture of the Unibond(R) SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart-Cut(R) process is described in detail and material characteristics of Unibond(R) wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

In the data path circuits of asynchronous systems, logical faults may first manifest as undetectable, transient wrong codewords, in spite of encoding the inputs and the outputs and proper organization which enables the faults to be propagated to the primary outputs in the form of non-codewords. Due to this, the conventional methods of concurrent error detection (CED) using the logic (voltage) monitoring is not effective. In this paper, we suggest a mixed-signal approach to achieve CED for a class of asynchronous circuits, known as self-timed circuits. First, we show that it is impossible to guarantee the CED using logic monitoring of the primary outputs in spite of proper encoding and organization of self-timed circuits. Then, we discuss different manifestations of single stuck-at faults occurring during normal operation in these circuits. Finally, we present the feasibility of achieving CED using a built-in current sensor (BICS) along with encoding techniques.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

In this paper, we extend the circuit partitioning algorithm which we have proposed for multi-FPGA systems and present a new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it. The core of the presented algorithm is recursive bipartitioning of a circuit. The bipartitioning procedure consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm computes the lower bounds of delays for paths with path delay constraints and detects the critical paths based on the difference between the lower and upper bound dynamically in every bipartitioning procedure. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary inputs and outputs on each critical path to one chip so that the critical path does not cross between chips. Finally in 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional alogorithms.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.

In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.