A quasi-optical Superconductor-Insulator-Superconductor (SIS) mixer has been designed and tested in the 270-GHz band. The mixer used a substrate-lens-coupled log-periodic antenna and a tuning circuit for RF matching. The antenna is planar and self-complementary, and has a frequency-independent impedance of around 114 Ω over several octaves. The tuning circuit consists of two Nb/AIOx/Nb tunnel junctions separated by inductance for tuning out the junction capacitances and a λ/4 impedance transformer for matching the resistance of the two-junction circuit to the antenna impedance. The IF output from the mixer is brought out in a balanced method at each edge of the antenna, and is coupled to a low noise amplifier through a balun transformer using a 180-degree hybrid coupler for broadband IF matching. Double sideband receiver noise temperatures, determined from experimental Y-factor measurements, are about 150 K across the majority of the desired operating frequency band. The minimum receiver noise temperature of 120 K was measured at 263 GHz, which is as low as that of waveguide receivers. At this frequency, measurement of the noise contribution to the receiver results in input losses of 90 K, mixer noise of 17 K, and multiplied IF noise of 13 K. We found that the major sources of noise in our quasi-optical receiver were the optical losses.

The objective of this paper is to find a parametric representation for the vocal-tract log-area function that is directly and simply related to basic acoustic characteristics of the human vocal-tract. The importance of this representation is associated with the solution of the articulatory-to-acoustic inverse problem, where a simple mapping from the articulatory space onto the acoustic space can be very useful. The method is as follows: Firstly, given a corpus of log-area functions, a parametric model is derived following a factor analysis technique. After that, the articulatory space, defined by the parametric model, is filled with approximately uniformly distributed points, and the corresponding first three formant frequencies are calculated. These formants define an acoustic space onto which the articulatory space maps. In the next step, an independent component analysis technique is used to determine acoustic and articulatory coordinate systems whose components are as independent as possible. Finally, using singular value decomposition, acoustic and articulatory coordinate systems are rotated so that each of the first three components of the articulatory space has major influence on one, and only one, component of the acoustic space. An example showing how the proposed model can be applied to the solution of the articulatory-to-acoustic inverse problem is given at the end of the paper.

This paper presents the results of a simulation study of blocking and non-blocking switching for hierarchical ring networks. The switching techniques include wormhole, virtual cut-through, and slotted ring. We conclude that slotted ring network performs better than the more popular wormhole and virtual cut-through networks. We also show that the size of the node buffers is an important parameter and that choosing them too large can hurt performance in some cases. Slotted rings have the advantage that the choice of buffer size is easier in that larger than necessary buffers do not hurt performance and hence a single choice of buffer size performs well for all system configurations. In contrast, the optimal buffer size for virtual cut-through and wormhole switching nodes varies depending on the system configuration and the level in the hierarchy in which the switching node lies.

Nonuniform traffic can degrade the overall performance of multistage interconnection networks substantially. In this paper, this performance degradation is traced back to blocking effects that are not present under uniform traffic patterns within a network. This blocking phenomenon is not mentioned in the literature and is termed higher order Head-of-Line-blocking (HOLk-blocking) in this paper. Methods to determine the HOL-blocking order of multistage networks in order to classify the networks are presented. The performance of networks under hot-spot traffic as a function of their HOL-blocking characteristics is studied by simulation. It is shown that network bandwidth and packet delay improve under nonuniform traffics with increasing HOL-blocking order of a network.

The medial axis transform (MAT) is an image representation scheme. For a binary image, the MAT is defined as a set of upright maximal squares which consist of pixels of value l entirely. The MAT plays an important role in image understanding. This paper presents a parallel algorithm for computing the MAT of an n n binary image. We show that the algorithm can be performed in O(log n) time using n2/log n processors on the EREW PRAM and in O(log log n) time using n2/log log n processors on the common CRCW PRAM. We also show that the algorithm can be performed in O(n2/p2 + n) time on a p p mesh and in O(n2/p2 + (n log p)/p) time on a p2 processor hypercube (for 1 p n). The algorithm is cost optimal on the PRAMs, on the mesh (for 1 p n) and on the hypercube (for 1 p n/log n).

The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).

This paper presents a method for mechanically transforming a parallel algorithm on an original network so that the algorithm can work on a target network. It is assumed that the networks are of cube-type such as the shuffle-exchange network, omega network, and hypercube. Were those networks isomorphic to each other, the algorithm transformation is an easy task. The proposed transformation method is based on a novel graphembedding scheme <φ: δ, κ, π, ψ>. In addition to the dilating operation δ of the usual embedding scheme <φ: δ>, the novel scheme uses three primitive graph-transformation operations; κ (= δ-1) for contracting a path into a node, π for pipelining a graph, and ψ (= π-1) for folding a pipelined graph. By applying the primitive operations, the cube-type networks can be transformed so as to be isomorphic to each other. Relationships between the networks are represented by the composition of applied operations. With the isomorphic mapping φ, an algorithm in a node of the original network can be simulated in the corresponding node(s) of the target network. Thus the algorithm transformation is reduced to routine work.

Efficient parallel algorithms for several problems on proper circular arc graphs are presented in this paper. These problems include finding a maximum matching, partitioning into a minimum number of induced subgraphs each of which has a Hamiltonian cycle (path), partitioning into induced subgraphs each of which has a Hamiltonian cycle (path) with at least k vertices for a given k, and adding a minimum number of edges to make the graph contain a Hamiltonian cycle (path). It is shown here that the above problems can all be solved in logarithmic time with a linear number of EREW PRAM processors, or in constant time with a linear number of BSR processors. A more important part of this work is perhaps the extension of basic BSR to allow simultaneous multiple BROADCAST instructions.

Physical optics(PO) and the aperture field integration method (AFIM) give accurate and similar field patterns near the first few sidelobes of reflector antennas. It is widely accepted that the use of AFIM is restricted to norrower angles than PO. In this paper, uniform equivalent edge currents of PO and AFIM are compared analytically and their equivalence in high frequency in discussed. It is asymptotically verified that the patterns by AFIM are almost identical to PO fields in the full 360angular region, provided that AFIM uses the equivalent surface currents consisting of two components, that is, the geometrical optics(GO) reflected fields from the reflector and the incident fields from the feed source, the latter of which are often neglected. Slightly weaker equivalence is predicted for cross polarization patterns. Numerical comparison of PO and AFIM confirms all these results, the equivalence holds not only for large but also for a very small refiector of the order of one wavelength diameter.

The mesh-connected computers with hyperbus broadcasting are an extension of the mesh-connected computers with multiple broadcasting. Instead of using local buses, we use global buses to connect processors. Such a strategy efficiently reduces the time complexity of the semigroup problem from O(N) to O(log N). Also, the matrix multiplication and the transitive closure problems are solved in O(log N) and O(log2 N) time, respectively. Then, based on these operations, several interesting problems such as the connected recognition problem, the articulation problem, the dominator problem, the bridge problem, the sorting problem, the minimum spanning tree problem and the bipartite graph recognition problem can be solved in the order of polylogarithmic time.

Motivated by the design of fault-tolerant multiprocessor interconnection networks, this paper considers the following problem: Given a positive integer t and a graph H, construct a graph G from H by adding a minimum number Δ(t, H) of edges such that even after deleting any t edges from G the remaining graph contains H as a subgraph. We estimate Δ(t, H) for the hypercube and torus, which are well-known as important interconnection networks for multiprocessor systems. If we denote the hypercube and the square torus on N vertices by QN and DN respectively, we show, among others, that Δ(t, QN) = O(tN log(log N/t + log 2e)) for any t and N (t 2), and Δ(1, DN) = N/2 for N even.

A new CMOS analogue transconductor is proposed and simulated. This transconductor is based on the operation of MOS transistors in the linear region and has a good linearity. The simulation result shows that less than 1% distortion can be obtained for the differential input signal of 6.4 Vp-p with IB=80µA and supply voltage of 5V.

Precise direct mounting of laser diode (LD) and photodiode (PD) chips on silica planar lightwave circuits (PLCs) has been investigated for application to transceiver modules. To achieve submicron optical alignment, self-aligned index marks on the PLCs and LDs were directly detected by transmission infrared light. The repeatability of the positioning was measured to be within 0.125 µm. The output power of the resultant module was 0.2 mW at 80 mA. A waveguide-type PD was also mounted in the same way, and module sensitivity of 0.25 A/W was demonstrated.

In this paper, a feasible optical code-division multiple-access (CDMA) technique is proposed for high-speed computer networks using prime codes and optical signal processing to guarantee real-time data communications. All-optical architectures for fastly tunable CDMA encoders and decoders are presented, which can be feasibly implemented in the optical domain by using electrooptic switches and optical delay lines. This can support an ultrahigh throughput and a very fast reconfiguration time. Furthermore, we present a self-synchronized sample technique to ensure the correct phase synchronization between optical clock stream and asynchronous electronic data at each electrooptic modulator of an optical CDMA transmitter.

We have devised a polynomial time algorithm to decide the security of cryptographic protocols formally under certain conditions, and implemented the algorithm on a computer as a supporting system for deciding the security. In this paper, a useful approach is presented to decide security problems which do not satisfy some of the above-mentioned conditions by using the system. For its application, we consider a basic security problem of Kerberos protocol, whether or not an enemy can obtain the session key between a client and a server by using any information not protected in communication channels and using any operation not prohibited in the system. It is shown that Kerberos is secure for this problem.

A new current-mode analog BiCMOS multiplier/divider circuit based on the translinear principle is presented. This circuit can be implemented by a standard 0.8µm BiCMOS process. The simulation results showed that the circuit realizes the high-speed and high-precision operation with a 3V supply.

During the last decade the decrease in the size of computing machinery, coupled with the increase in their computing power has lend to the development of the concept of mobile computing. Effects of this new vision is currently evident in the flourishing numbers of mobile telephones and portable computing units. In this paper we briefly investigate some issues concerning the security of mobile computing systems, within the framework of the categories of mobility, disconnection, data access modes and scale of operation (Imielinski & Badrinath, 1993). In contrast to previous works which concentrate on security in wireless communications, we focus on the security of interactions which are built upon the underlying wireless communications medium. Some conclusions are presented on the future directoins for security research in mobile computing sysytems.

The n-dimensional hypercube is a highly concurrent loosely coupled multiprocessor based on the binary n-cube topology. This paper is concerned with the following basic graph-theoretic question: given a graph G = (V, E), is it an exact n-cube? We propose an O (|E|) hypercube recognition algorithm using some new topological properties of the hypercube graph.

A structural active-object system (SAOS) is a transition-based object-oriented system suitable for rapid development of hardware logic simulators. A SAOS consists of a collection of interacting structural active objects (SAOs), whose behaviors are determined by the transition statements provided in their class definitions. Furthermore, SAOs can be structurally and hierarchically composed from their component SAOs like hardware components. These features allow SAOs to model components for circuit simulation more naturally than passive objects used in ordinary object-oriented programming. Also, we can easily create new kinds of components by using the inheritance mechanism. Executions of transition statements may be event-and/or time-driven, and hence digital, analog, and mixed-mode simulation is possible. Prototype simulation programs with graphical user interfaces have been developed as SAOS programs for digital, analog, and mixed-mode circuit simulation.

The data retention characteristics for Flash EEPROM degrade after a large number of write and erase cycles due to the increase of the tunnel oxide leakage current. This paper proposes a new write/erase method which uses a reverse polarity pulse after each erase pulse. By using this method, the leakage current can be suppressed. As a result, the read disturb time after 105cycles write/erase operation is more than 10 times longer in comparison with that of the conventional method. Moreover, using this method, the endurance cycle dependence of the threshold voltage after write and erase operation is also drastically improved.