This paper proposed a practical method of program validation for state-based reactive concurrent systems. The proposed method is of particular relevance to plant control systems. Plant control systems can be represented by extended state transition systems (e.g., communicating asynchronous transition systems). Our validation method is based on state space analysis. Since naive state space analysis causes the state explosion problem, techniques to ease state explosion are necessary. One of the most promising techniques is the partial order method. However, these techniques usually require some structural assumptions and they are not always effective for actual control systems. Therefore, we claim integration and harmonization of verification (i.e., state space analysis based on the partial order method) and simulation (i.e., conventional validation technique). In the proposed method, verification is modeled as exhaustive simulation over the state space, and two types of simulation management techniques are introduced. One is logical selection (pruning) based on the partial order method. The other is heuristic selection based on priority (a priori precedence) specified by the user. In order to harmonize verification (logical selection) and conventional simulation (heuristic selection), we propose a new logical selection mechanism (the default priority method). The default priority method which prunes redundant state generation based on default priority is in harmony with heuristic selection based on the user's priority. We have implemented a practical validation tool, Simulation And Verification Environment for Reactive Concurrent Systems (SAVE/RCS), and applied it to chemical plant control systems.

A graph G = (V, E) with N nodes is called an N-hyper-ring if V = {0, ..., N-1} and E = {(u, v)(u-v) modulo N is power of 2}. We study embeddings of the 2n-hyper-ring in the n-dimensional hypercube. We first show a greedy embedding with dilation 2 and congestion n+1. We next modify the greedy embedding, and then we obtain an embedding with dilation 4 and congestion 6.

As Object-Oriented Database Systems (OODBS) play an increasingly important role in advanced database systems, OODBS performance becomes a significant issue. It is well known that there is a strong relationship between performance and the concurrency control algorithms employed by the Database Management System (DBMS). Class Granularity Locking (CGL) and Class Hierarchy Granularity Locking (CHGL) are proposed as the concurrency control algorithms for OODBS to minimize the locking overhead. However, their basic characteristics, including the licking overhead and concurrency, have not been extensively investigated and it is not known which one is most appropriate for the general case. In this paper, we construct a simulation model for OODBS and carry out several performance evaluation studies on these two Class-Hierarchy Locking protocols and the Non Class-Hierarchy Locking (NCL) protocol. The NCL protocal is a variation of the conventional two phase locking protocol being applied to OODBS data structures.

A fully-differential switched-current (SI) circuit provided with clock-feedthrough (CFT) and common mode rejection and offset compensation schemes is described. Different from a conventional SI memory cell, it takes the difference between two differential inputs to deliver the balanced differential currents. Transistor level simulations and error analyses are given to demonstrate its performance.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

A soft magnetic force microscope (MFM) tip was used to evaluate the magnetic recording characteristics of compositionally separated Co-Cr perpendicular media. Small magnetic bits were recorded on thick (350 nm). and thin (100 nm) films, focusing on the fineness of compositionally separated microstructures. MFM images showed bit marks 230 and 150 nm in diameter, measured at full-width at half maximum (FWHM) for the thick and thin films, respectively. These results verify that the recordable bit size can be decreased by using a thinner film with a finer compositionally separated microstructure. Simulation was used to clarify the relationship between the actual sizes of the recorded bits and the sizes of their MFM images. The recorded bit size was found to closely correspond to the FWHM of the MFM bit images.

In this paper, the diffusion parameter-values in the K+-ion diffused waveguides made by diluted KNO3 with NaNO3 in the soda-lime glass, which are determined from measured values of the effective index, are presented together with a simple method for the determination. The surface-index changes are measured for the waveguides by KNO3 melts with 75%-, 50%- and 30%-dilutions (weight ratio), and for comparison purpose, also by the pure KNO3, and the dependence of the index-profile on the dilution of KNO3 in the ion-source melt is shown. Change of the two-dimensional index profile in the diffused channel waveguide with the KNO3-dilution is also shown, which is calculated with the measured diffusion parameters.

Considered is the theory of several dielectric waveguide phenomena for which the vector nature of the electromagnetic field is essential. These phenomena are the following rotation of the plane of polarization in chiral and twisted waveguides, Bragg's reflection in a twisted waveguide in a narrow frequency band, and excitation of a waveguide at a near-cutoff frequency.

We propose an equivalent circuit model described by the Rössler equation. Then we can consider a coupled Rössler system with a physical meaning on the connection. We consider an oscillatory circuit such that two identical Rössler circuits are coupled by a resistor. We have studied three routes to entirely and almost synchronized chaotic attractors from phase-locked periodic oscillations. Moreover, to simplify understanding of synchronization phenomena in the coupled Rössler system, we investigate a mutually coupled map that shows analogous locking properties to the coupled Rössler System.

This paper describes an MOS charge-mode version of a T-Model neural-based PCM encoder. The neural-based PCM encoding networks are designed, simulated and implemented using MOS charge-mode circuits. Simulation results are given for both the T-Model and the Hopfield model CMOS charge-mode PCM encoders, and demonstrate the T-Model neural-based one performs the PCM encoding perfectly, while the Hopfield one fails to.

Secure communications via chaotic synchronization is experimentally demonstrated using 3-pieces of commercial integrated circuit phase-locked loops, MC14046. Different from the conventional chaotic synchronization secure communication systems where one channel is used, our system uses two channels to send one signal to be concealed. Namely, one channel is used to send a synchronizing chaotic signal. The other channel is used to send the informational signal superimposed on the chaotic masking signal at transmitter side. The synchronizing chaotic signal is applied as a common input to two identical PLL's located at both transmitter and receiver sides. It has been shown previously by us that the VCO inputs of almost identical two PLL's driven by a common chaotic signal become chaotic, and synchronized with each other. This synchronization is only possible for those who knows exact internal configuration and exact parameter values of the PLL at transmitter side. Therefore, we can use the synchronized VCO input signal as a masking signal which can be used as a key for secure communications. The advantage of this method compared to the previous one channel method is that informational signal frequency range does not affect the quality of recovered signal. Our experiments demonstrate good masking and recovery characteristics for sinusoidal, triangular, and square waves.

In this paper, a new switched-current auto-tuning filter is proposed. Switched-current (SI) is a current-mode analog sampled-data circuit technique. An SI circuit can be realized using only standard digital CMOS technologies, and is capable of realizing high frequency circuits. The proposed filter is composed of SI-OTA (operational transconductance amplifier) integrators. The gain of an SI-OTA integrator can be electronically controlled by the bias current. The proposed filter is a current controlled filter (CCF) and a PLL technique was used as its tuning method. A 2nd-order SI auto-tuning low-pass filter with 100kHz cutoff frequency was designed assuming a 2µm CMOS process. The characteristics of this SI filter and its tuning characteristics were confirmed by SPICE simulations.

On a simple model, the quality of the security tag is simulated theoretically and experimentally. A simple correction makes both results correspond exactly and a simulation formula is provided. By using novel insulating film, a small-sized tag of high quality is developed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

In this paper, we analyze the traffic data management requirements of the customers, describe the functions of the traffic database needed to satisfy their requirements, and propose a highly distributed database system which can efficiently implement these functions. Finally, we report the results of system performance evaluations.

We have developed a 15-Gbit/s 96-gate Si-bipolar gate array using 0.5-µm Si-bipolar technology, a sophisticated internal cell design, an I/O buffer design suitable for high-speed operation and high-frequency package technology. The decision circuit and 4 : 1 multiplexer fabricated on the gate array operate up to 15-Gbit/s and above 10-Gbit/s respectively. The data input sensitivity and the phase margin of the decision circuit are 53 mVpp and 288 at 10-Gbit/s operation. This gate array promises to be useful in shortening the development period and lowering cost of 10-Gbit/s class IC's.

Schnorr's identification scheme is the most efficient and simplest scheme based on the discrete logarithm problem. Unfortunately, Schnorr's scheme is not provably secure, i.e., the security has not been proven to be reducible to well defined intractable problems. Two works have already succeeded to construct provably secure variants of Schnorr's scheme. They have been constructed with a common approach, i.e., by modifying the formula to compute the public key so that each public key has multiple secret keys. These multiple secret keys seem to be essential for their provable security, but also give rise to a penalty in their efficiency. In this paper, we describe a new approach to constructing a provably secure variant, where we never modify the formula, and show that with our approach, we can construct a new efficient provably secure scheme.

In this paper we present a system for secure communications based on chaos synchronization. Unlike the existing systems for communication via chaotic synchronization, our system extracts the information at the receiver without error. A possibility for secure communications using Lorenz system is given. A practical algorithm for secret-key cryptography is suggested and is evaluated through statistical tests that have not shown any weakness. Furthermore, the algorithm is extremely simple for implementation in a program.

We study all-to-all broadcasting in hypercubes with randomly distributed Byzantine faults. We construct an efficient broadcasting scheme BC1-n-cube running on the n-dimensional hypercube (n-cube for short) in 2n rounds, where for communication by each node of the n-cube, only one of its links is used in each round. The scheme BC1-n-cube can tolerate (n-1)/2 Byzantine faults of nodes and/or links in the worst case. If there are exactly f Byzantine faulty nodes randomly distributed in the n-cabe, BC1-n-cube succeeds with a probability higher than 1(64nf/2n) n/2. In other words, if 1/(64nk) of all the nodes(i.e., 2n/(64nk) nodes) fail in Byzantine manner randomly in the n-cube, then the scheme succeeds with a probability higher than 1kn/2. We also consider the case where all nodes are faultless but links may fail randomly in the n-cube. Broadcasting by BC1-n-cube is successful with a probability hig her than 1kn/2 provided that not more than 1/(64(n1)k) of all the links in the n-cube fail in Byzantine manner randomly. For the case where only links may fail, we give another broadcasting scheme BC2-n-cube which runs in 2n2 rounds. Broadcasting by BC2-n-cube is successful with a high probability if the number of Byzantine faulty links randomly distributed in the n-cube is not more than a constant fraction of the total number of links. That is, it succeeds with a probability higher than 1nkn/2 if 1/(48k) of all the links in the n-cube fail randomly in Byzantine manner.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.