Switched-capacitor chaotic neurons fabricated in a full-custom integrated circuit are used to investigate the behavior of 2- and 3-neuron chaotic neural networks. Various sets of parameters are used to visualize the dynamical responses of the networks. Hysteresis of the network is also demonstrated. Lyapunov exponents are approximated from the measured data to characterize the state of each neuron. The effect of the finite length of data and the rounding effect of data acquisition system to the computation of Lyapunov exponents are briefly discussed.

First, the necessity of examining the numerical calculation of the Bessel function Jν(x) of complex order ν is explained. Second, the possibility of the numerical calculation of Jν(x) of arbitrary complex order ν by the use of the recurrence formula is ascertained. The rounding error of Jν(x) calculated by this method is investigated next by means of theory and numerical experiments when the upper limit of recurrence is sufficiently large. As a result, it was known that there is the possibility that the rounding error grows considerably when ν is complex. Counterplans against the growth of the rounding error will be described.

A 10-kW (53V/200A), forced-air-cooled DC-DC converter has been developed for fuel cell systems. This converter uses new high-voltage bipolar-mode static induction transistors (BSIT), a new driving method, a zero-voltage-switched pulse-width-modulation technique, and a new litz wire with low AC resistance. It weighs only 16.5kg, has a volume of 26,000cm3, operates at 40kHz, and has a power conversion efficiency of about 95%. The power loss of this converter is 20% less than that of conventional natural-air-cooled DC-DC converters, and the power density is 3 times as high.

As a first step to develop a system to analyze or recognize patterns contained in mages, it is important to provide a good base representation that can facilitate efficiently the interpretation of such patterns. Since structural features of basic patterns in document images such as characters or tables are horizontal and vertical stroke components, we propose a new expression of document image based on the MCR expression that can express well such features of text and tabular components of an image.

A Hierarchical Cubic Network (HCN) is a hierarchical hypercube network proposed by Ghose. The HCN is topologically superior to many other similar networks, in particular, the hypercube. It has a considerably lower diameter than a comparable hypercube and is realized using almost half the number of links per node as a comparable hypercube. In this paper, we propose the shortest routing algorithm in HCN(n, n) and show that the diameter of HCN(n, n) with 22n nodes is n(n1)/31 which is about 2/3 of that of a comparable hypercube. We also propose the optimal routing algorithm in HCN(m, n) where mn and obtain that its diameter is n(m1)/31. Typical parallel algorithms run in HCN(m, n) with the same time complexity as a hypercube and the hypercube topology can be emulated with O(1) time complexity in it.

A multiple instruction stream-multiple data stream (MIMD) computer is a parallel computer consisting of a large number of identical processing elements. The essential feature that distinguishes one MIMD computer family from another is the interconnection network. In this paper, we are concerned with a representative type of interconnection networks: the hypercube connected network. A family of regular graphs is presented as a possible candidate for the implementation of a distributed system and for fault-tolerant architectures. The symmetry of graphs makes it possible to determine message routing by using a simple distributed algorithm. A candidate having the same property is the hypercube connected network. Arbitrary data permutations are generally accomplished by sorting. For certain classes of permutations, however, this is, for many frequently used permutations in parallel processing such as bit reversal, bit shuffle, bit complement, matrix transpose, butterfly permutations used in FFT algorithms, and segment shuffles, there exist algorithms that are more efficient than the best sorting algorithm. One such class is the bit permute complement (BPC) class of permutations. In this paper, we, first, develop an algorithm to realize an arbitrary BPC permutation in hypercube connected networks. The developed algorithm in hypercube connected networks requires only 1 token memory register in each node. We next evaluate the ability to realize BPC permutations in these networks of an arbitrary size by estimating the number of required routing steps.

The state of the art of low-voltage (LV) analog circuit design techniques is reviewed, and fundamental design techniques are identified and classified as follows: 1) current-mode, 2) series-to-parallel, 3) signal range sharing, 4) dynamic bias, 5) linear bias, and 6) LV regulator. A relatively wide variety of low frequency application circuits have been developed, but future development is expected for wide-bandwidth application circuits such as a voltage-controlled-oscillator (VCO), a balanced multiplier, etc. The circuit techniques such as current-mode, signal range sharing, and dynamic bias will probably be most important for advanced future circuit designs.

The recent progress of B-ISDN signaling systems has enabled networks to handle calls which require a wide variety of ATM connection sets. This paper is concerned with the circuit group which handles calls requesting asymmetric forward and backward multi-connections, and has the capability of both bandwidth negotiation and bandwidth reservation as a traffic control for enhancing call blocking performance. A model of the circuit group is first established focusing on the call level characteristics of the group, and then a method based on the reduced load approximation and an approximate analysis of a multirate group is proposed for calculating approximate blocking probabilities. The accuracy of the approximation method is evaluated numerically by comparing with an exact method and simulation. Further the impact of bandwidth negotiation and reservation on call blockings is examined based on numerical examples.

In this paper, we present a method for extracting the Japanese printed characters from unformatted document images. This research takes into account the multiple general features specific to the Japanese printed characters. In our method, these features are thought of as the constraints for the regions to be extracted within the constraint satisfaction approach. This is achieved by minimizing a constraint function estimating quantitative satisfaction of the features. Our method is applicable to all kinds of the Japanese documents because it is no need of a priori knowledge about the document layout. We have favorable experimental results for the effectiveness of this method.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

In this paper we introduce a new feature called stroke index for document image analysis. It is based on the minimum covering run expression method (MCR). This stroke index is a function of the number of horizontal and vertical runs in the original image and of number of runs by the MCR expression. As document images may present a variety of patterns such as graph, text or picture, it is necessary for image understanding to classify these different patterns into categories beforehand. Here we show how one could use this stroke index for such applications as classification or segmentation. It also gives an insight on the possibility of stroke extraction from document images in addition to classifying different patterns in a compound image.

B-ISDN telecommunication systems will require signal processing speeds up to 600 Mbps or more. We must therefore consider the affects of signal reflection, signal attenuation, time dalay, and so on when designing these systems. The higher the signal speed, the larger the electrical noise induced around the connector, especially in the plated through holes (PTHs) area. This paper presents the results of our investigation focused on connector mounting configurations in the signal transmission line, especially whether or not signals transmit through the PTH in a printed circuit board (PCB). How the signal reflection characteristics depend upon transmission line configurations are discussed and experimental results and simulation analyses for a transmission line system using a small miniature A-type (SMA) connector as an example are performed. It is suggested that designs for future high-speed signal transmission circuits take into account the PTH diameter and/or the PTH pitch conditions, values for which can be determined from simulation analysis.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

In this paper, we demonstrate how Yamakawa's chaotic chips and Chua's circuits can be used to implement a secure communication system. Furthermore, their performance for the secure communication is discussed.

Circuit access control is a traffic control technique of rejecting calls arriving at a group of specified circuits to make the group free at a target scheduled time so that the capacity may be dynamically reallocated to serve other traffic demand. This technique plays an important role for resource allocation control in state-of-the-art capacity reconfigurable networks as well as for switching calls on a reserved basis in the ISDNs. In this paper, we present a novel adaptive scheme for circuit access control in order to overcome the inefficiency of the conventional deterministic scheme. The presented scheme is based only on knowledge about service time and bandwidth characteristics of calls. The transitional behavior of the circuit group under the scheme is analyzed, and the gain in utilization achieved by the adaptive scheme is examined. We treat a model of the circuit group shared by multi-slot calls with different service times, and describe the results of the transient analysis and the approximation method for evaluating the gains.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

In this paper, we describe a worst-case design optimization approach for statistical design of integrated circuits with a circuit performance model scheme. After formulating worst-case optimization to an unconstrained multi-objective function minimization problem, a new objective function is proposed to find an optimal point. Then, based on an interpolation model scheme of approximating circuit performance, realistic worst-case analysis can be easily done by Monte Carlo based method without increasing much the computational load. The effectiveness of the presented approach is demonstrated by a standard test function and a practical circuit design example.

We discuss properties of acyclic graph evolution driven by node-firing. The research background and basic concepts of acyclic graph evolution are from the mutual exclusion problem in distributed environments. We proposed in our previous work a mutual exclusion protocol which is based on the notion of evolution trajectories of acyclic graphs. In this paper, we analyze firing concurrency and periodicity of the acyclic graph evolution, from graph theoretical point of views, and investigate topological conditions for assuring the number of firable nodes below a some fixed constant, at any instance of the evolution trajectory. A marked graph, a subclass of Petri nets, is often utilized as a proof tool in analysis.

It has become very important to study the lightning surges that were induced in subscriber telecommunication equipment because of the increase of susceptible circuits to the over voltage. The test generator is desire to be developed evaluating the resistibility of equipments against lightning surges. This paper proposes a new lightning-test method for subscriber telecommunication equipment. The waveform of the test generator simulates that of the induced lightning surge voltage caused by a nearby return stroke. The output impedance of the surge generator is determined to match the common-mode impedance of telecommunication lines. The damaged condition of circuit parts and the trouble occurrence rate estimated by using this method agree well with actual observations.