This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

In the design and analysis of circuit-switched alternate-routing networks a fundamental and important problem is the decomposition of the overflow traffic from a given trunk-group (or link) into its component traffic streams. Decomposition is required because the individual streams corresponding to different sources of traffic can in principle be routed to different links depending upon the routing algorithms. Because the exact solution of this problem is intractable, several approximate methods have been given in the past. However, these approximate methods yield either incomplete solutions or solutions that are not tractable enough to be implementable in today's large networks. In this paper, we describe a model which provides a complete solution for the individual streams overflowing a group of trunks when this group of trunks is offered a number of independent traffic streams with varying peakedness values (peakedness=variance/mean, where mean and variance are the first two moments of a given traffic stream (or distribution); these moments adequately describe a given traffic distribution for teletraffic calculations). The derived formulas are simple and easily implementable in algorithms for the design of today's networks which can require large amounts of computation.

In the information engineering learning environment, there may be more than one solution to any given problem. We have developed CAMELOT using the Nominal Group Technique for group problem solving. This paper describes the collaborative learning system on the Internet using discussion model, the effectiveness of collaborative learning in modeling the entity-relationship diagram within the field of information engineering, and how to apply AI technologies such as rule-based reasoning and case-based reasoning to the pedagogical strategy. By using CAMELOT, each learner learns how to analyze through case studies and how to collaborate with his or her group in problem solving. As a result. We have found evidence for the effectiveness of collaborative learning, such as getting a deeper understanding by using CAMELOT than by individual learning, because they can reach better solutions through discussion, tips from other learners, examination of one another's individual solutions, and understanding alternative solutions using case-based reasoning.

For object analysis and recognition, an original shape often needs to be described by using a small number of vertices. Polygonal approximation is one of the useful methods for the description. In this paper, we propose the curvature-based polygonal approximation (CBPA) method that is an application of the weighted polygonal approximation problem which minimizes the number of vertices of an approximate curve for a given error tolerance (the weighted minimum number problem). The CBPA method considers the curvature information of each vertex of an input curve as the weight of the vertex, and it can be executed in O(n2) time where n is the number of vertices of the input curve. Experimental results show that this method is effective even in the case when relatively few vertices are given as an original shape of a planar object, such as handwritten letters, figures (freehand curves) and wave-form data.

A formal system-level synthesis model for the concurrent object-oriented design of parallel computer systems, called Multi-token Object-oriented Bi-directional net (MOBnet), is proposed. The MOBnet model extends the standard Petri net by defining (1) multiple tokens to represent different kinds of synthesis control information, (2) object-oriented nodes (places) to denote the system parts under synthesis, and (3) bi-directional arcs to model the design completion check and synthesis rollback operations. In this paper, we first show that MOBnet can serve as a pre-fabrication design methodology analysis tool in ways such as class hierarchy construction, design specification comparison, reachability analysis, and concurrent process management and analysis. We then formally prove MOBnet to be a valid model for concurrent synthesis and give experimental application examples to verify. Finally, solution schemes for the design completion check and synthesis rollback problems are formally validated by analyzing the dynamic behavior of MOBnet, and experimentally illustrated through examples.

This paper is concerned with two important planning problems for transport network planning; circuit routing problems and facility planning problems. We treated these optimization problems by taking into account survivability requirements. In the circuit routing problem tackled in this paper, therefore, optimization of circuit restoration plans, namely allocation of spare capacity for assumed failure scenarios is considered together with optimization of circuit routing in a no failure case. In the facility planning problems, failure scenarios of new facilities whose installation is yet to be determined are considered. In this paper, we present a formulation of these two optimization problems, and give 1) optimization algorithms based on the IA (Increment Assignment) method for routing problems and 2) optimization algorithms based on a combination of the GA (Genetic Algorithm) and the IA method for facility planning problems. The IA based routing algorithm can cope flexibly with various constraints on practical network operations and is applicable to large-scale complicated network models without causing a rapid increase in computation time. The GA based facility planning algorithm includes the IA based algorithm as a function for evaluating objective function values. Taking advantage of the important features of the IA based algorithm, we propose an acceleration technique for the GA based facility planning algorithm. In this paper, several numerical examples are provided and the effectiveness of the proposed algorithms is numerically evaluated.

Narrow-band ISDN services may experience nonstationary traffic conditions. Therefore, switch design should take account of these conditions. We propose new performance measures for switching systems and describe a traffic model, which is a mixture of stationary Poissonian traffic and momentarily focused traffic. On the basis of this model, performance measures are determined so as to satisfy grade of service requirements that are in effect during some short interval after the momentarily focused traffic enters the system. We also propose an overload control scheme that uses these new performance measures. Finally, we show practical and numerical examples for the performance measures and overload control scheme.

In recent years, and increasing number of studies have been reported regarding multimedia LANs that integrate voice, data and video communications. The Movable Boundary method has been suggested as a way to integrate circuit and packet switching. However, how this can be practically managed, especially for multimedia LANs, is not clear. Working under the assumption that an optical loop network in used as a multimedia LAN, we propose Hybrid Allocation as a new Movable Boundary method. Hybrid Allocation features traffic prediction for circuit switching calls, and timeslot allocation close to the boundary of circuit and packet switching areas. Evaluations of traffic simulation and network efficiency show it to be a promising architecture for integrating circuit and packet switching on a multimedia LAN.

We present a current mode cyclic analog-to-digital converter that is suitable for submicron LSI fabrication processes. Our converter is composed of sample-and-hold circuits with regulated cascode configuration which offers high output impedance and wide outoput range. The circuit requires small area since the architecture depends on neither precise analog transistors nor ratio-matched capacitors. We have designed and fabricated a test circuit that has an area of 0.014mm2 using a 0.8µm CMOS process. The circuit is examined to perform 8-bit resolution at a sampling rate of 40kHz and average power dissipation of 370µW at 4V supply voltage.

We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.

A CMOS programmable gain amplifier (PGA) with a swiched capacitor offset compensation circuit is described. The mean compensation error is 130µV at the input, and the standard deviation of the compensation error is 50µV. This PGA is applicable to a baseband amplifier for digital radio communication terminals.

A new structure for adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error is introduced and the mathematical background for the soulution of the related adaptive filtering problem is derived. The presented structure gives rise to AR spectral estimates that represent the true underlying spectrum with better fidelity than conventional LS methods by allowing an arbitrary trade-off between variance of spectral estimates and tracking ability of the estimator along the frequency spectrum. The linear prediction error is decomposed through a filter bank and components of each band are analyzed by different window lengths, allowing long windows to track slowly varying signals and short windows to observe fastly varying components. The correlation matrix of the input signal is shown to satisfy both time-update and order-update properties for rectangular windowing functions, and an RLS algorithm based on each property is presented. Adaptive forward and backward relations are used to derive a mathematical framework that serves as a basis for the design of fast RLS alogorithms. Also, computer experiments comparing the performance of conventional and the proposed multi-band methods are depicted and discussed.

This letter presents a realization of active current-mode resonator with complex coefficients using CCIIs. The resonator can be used for cascade or leapfrog configuration of high-order bandpass filters with complex coefficients. For realizing the resonators, only the grounded capacitors and the grounded resistors as passive elements are required, therfore the resonator is suitable for the integrated circuit realization. The letter shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of voltage-mode counterpart. Experimental result is used for verifying the feasibility of the proposed resonator.

Force curves obtained from an elastic contact theory are shown and compared with experimental results. In the elastic contact theory, a pin-on-disk contact is assumed and the following interaction are taken into consideration; (i) elastic deformation, (ii) the specific energy of adhesion in the area of the contact, which is expressed as the difference between the surface energies and the interface energy, (iii) the long-range interaction outside the area of contact, assuming the additivity of the Lennard-Jones type potential, and (iv) another elastic term for the measurement system such as the cantilever stiffness of an atomic force microscope (AFM). In the limit when the stiffness is infinite, the theory conforms to Muller-Yushchenko-Derjaguin (MYD) theory. In the limit when the surface-surface interaction is negligible, the theory conforms to the analytical theory by Takahashi-Mizuno-Onzawa. In the limit when the stiffness is infinite and the long-range interaction outside the area of contact is negligible, the theory conforms to Johnson-Kendall-Roberts (JKR) theory. All parameters and all equations are normalized and the normalized force curve is obtained as the functional of only two parameters; (1) the normalized stiffness of the measurement system, and (2) the normalized distance which is used in the expression of the Lennard-Jones potential. The force-displacement plots are converted into force-penetration plots.

In this paper, two types of improved CMRR CMOS OAs, N type and P type, without common-mode feedback and the cascode current mirrors, are proposed. The CMRR of proposed OAs are enhanced by compensating variations in tail bias current, caused by a common mode input signal, at the differential input stage, by means of feedforward controlled current source. Simulation results show that the CMRR of the proposed OAs are 20dB higher than that of conventional OAs.

In accordance with the diffusion of applications, such as the Desk Top Publishing system, the Document Formatting system and the Document Editing system, it is easy to make a document by using a computer. However, as for allocating the diagrams (figures and tables), there are few document processing systems able to allocate diagrams on the appropriate places automatically. In a document processing system it is a very important issue to allocate diagrams on the most suitable places. This paper defines the criteria for allocating diagrams on the suitable positions by investigating published papers. These criteria concern 1) the order of diagrams to be allocated, 2) the stability of the diagram allocations, 3) the distance between the diagram and the location of the corresponding first reference in the text, 4) the allocation balance of diagrams in a text, 5) the restricted areas where diagrams shouldn't be allocated, 6) the allocation priorities between diagrams of different width. Moreover, this paper proposes a method for deciding the diagram allocations satisfying the above criteria automatically and fast on document formatting systems. In this case we have limited its application to one type of ducuments, which is papers. Especially, this method can skillfully allocate diagrams of different width on the page by reallocating the diagrams and texts within it, and can allocate diagrams over the document uniformly.

High-end graphic systems with 3 million pixels require 8-bit D/A converters with more than 300-MS/s conversion rate. Furthermore, D/A converters need to operate with low supply voltage when they are integrated with large-scale digital circuits on a harf-micron CMOS process. This paper describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source circuit with a delayed driving scheme is developed. This driving scheme reduces a fluctuation of internal node voltage of the current source circuit and high-speed swiching is realized. In addition to this driving scheme, two stages of latches are inserted into matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-µm CMOS process with single poly-silicon layer and double aluminum layers. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

In this paper an analog CMOS implementation of Approximate Identity Neural Networks is suggested. In particular a one-input one-output Neural Network with 6 neurons has been designed and fabricated with a 2µm CMOS technology. Due to the small area occupied the circuit proposed for the neuron is suited for the implementation of larger networks.

In this paper, we apply the method of relating learning to hypothesis testing [6] to study average generalization performance of concept learning from noisy random training examples. A striking aspect of the method is that a learning problem with a so-called ill-disposed learning algorithm can equivalently be reduced to a simple one, and for this simple problem, even though a direct and exact calculation of the learning curves might still be impossible, a thorough empirical study can easily be performed. One of the main advantages of using the illdisposed algorithm is that it well models lower quality learning in real situations, and hence the result can provide useful implications as far as reliable generalization is concerned. We provide empirical formulas for the learning curves by simple functions of the noise rate and the sample size from a thorough empirical study, which smoothly incorporates the results from noise-free analysis and are quite accurate and adequate for practical applications when the noise rate is relatively small. The resulting learning curve bounds are directly related to the number of system weights and are not pessimistic in practice, and apply to learning settings not necessarily within the Bayesian framework.