In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

A design of current-mode continuous-time filters for low voltage and high frequency applications using complementary bipolar current mirror pairs is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integration. Since the filters are based on the integrator type of realization, the proposed method can be used for a wide range of applications. The frequency of the filters can easily be changed by the DC controlling current. A fifth-order Butterworth and a thirdorder leapfrog filter with tunable cutoff frequencies from 20 MHz to 100 MHz are designed as examples and simulated by SPICE using standard bipolar parameters.

A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 510-17 A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.

In this study, multimode chaos observed from two coupled chaotic oscillators with hard nonlinearities is investigated. At first, a simple chaotic oscillator with hard nonlinearities is realized. It is confirmed that in this chaotic oscillator the origin is always asymptotically stable and that the solution, which is excited by giving relatively large initial conditions, undergoes period-doubling bifurcations and bifurcates to chaos. Next, the coexistence of four different modes of oscillations are observed from two coupled chaotic oscillators with hard nonlinearities by both of circuit experiments and computer calculations. One of the modes of oscillation is a nonresonant double-mode oscillation and this oscillation is stably generated even in the case that oscillation is chaotic. Namely, for this oscillation mode, chaotic oscillation and periodic oscillation can be simultaneously excited. This phenomenon has not been reported yet, and we name this phenomenon as double-mode chaos. Finally, the beat frequency of the double-mode chaos is confirmed to be changed by varying the value of the coupling capacitor.

Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

In this paper, we give a direct proof of the result of Latteux and Turakainen that the full class of recursively enumerable languages can be obtained from minimal linear languages (which are generated by linear context-free grammars with only one nonterminal symbol) by Dyck reductions (which reduce pairs of parentheses to the empty word).

New series expressing the radiation fields from both axial and circumferential slots on a circular conducting cylinder are derived. These new series converge rapidly even for near fields. This letter includes useful figures showing characteristics of near fields calculated numerically using the new series.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

We present a recursive algorithm for constructing linear discrete-time systems which interpolate the desired 1st-and 2nd-order information. The recursive algorithm constructs a new system and connects it to the previous system in the cascade form every time new information is added. These procedures yield a practical realization of all the interpolants.

In this paper we analyze the reliability of a simple broadcasting scheme for hypercubes (HCCAST) with random faults. We prove that HCCAST (n) (HCCAST for the n-dimensional hypercube) can tolerate Θ(2n/n) random faulty nodes with a very high probability although it can tolerate only n - 1 faulty nodes in the worst case. By showing that most of the f-fault configurations of the n dimensional hypercube cannot make HCCAST (n) fail unless f is too large, we illustrate that hypercubes are inherently strong enough for tolerating random faults. For a realistic n, the reliability of HCCAST (n) is much better than that of the broadcasting algorithm described in [6] although the latter can asymptotically tolerate faulty links of a constant fraction of all the links. Finally, we compare the fault-tolerant performance of the two broadcasting schemes for n = 15, 16, 17, 18, 19, 20, and we find that for those practical valuse, HCCAST (n) is very reliable.

Access control has been an important security issue in information systems. Multilevel hierarchical information access widely exists in present-day government, military, and business applications. Extending access control design to work in a hierarchical environment is natural and necessary but rarely addressed so far in the literature. In this paper, a dynamic group-oriented cryptographic scheme to access a multilevel data hierarchy is proposed. In the proposed scheme, a trusted central authority is in charge of the administrative activities among the organization hierarchy. At the beginning, each user class submits its associated information and a cryptographic key of its preference to the central authority. Next the central authority generates a public information for each class according to their location in the organization hierarchy. The cryptographic key held by each class can be used directly as an encryption key to encipher data. These keys need not be modified when adding/deleting a class to/from the system. Compare with other existing schemes, ours has the advantages of flexibility in choosing user preferred cryptographic keys, cryptographic keys not exceeding a fixed length, reduced storage space in publishing pubic information, and protection from conspiracy attack.

This paper describes a novel shared file system, whose main features are enhanced security and its concurrency control mechanism. The system is especially suitable for access from mobile hosts. Users can edit their shared files concurrently. Shared files are encrypted and decrypted only by clients, and the file server cannot know the contents. The server asynchronously receives the edited parts, which are already encrypted, and merges them into the current version, deciphering neither the stored file nor the encrypted editing data. We call the mechanism 'privacy enhanced merging'. The mechanism and the underlying encryption algorithm, shared file data structure and procedures followed by clients and the server are shown.

This paper proposes a new RSA-type scheme over non-singular parts of singular cubic curves En(α,β):(y-αx)(y-βx)x3(mod n). In usual one-to-one communication, we prove that breaking the proposed scheme is not easier than breaking the RSA scheme for the whole ciphertexts. If encryption key e is larger than 19 for 512 bits modulus n, then the proposed scheme is secure against the Hastad attack in broadcast applications. A plaintext of two blocks, i.e., x and y coordinates in En(α,β), is encrypted to a ciphertext of three blocks, where the size of one block is log2n bits. The decryption speed ofthe proposed scheme is as fast as that of the RSA scheme for the even block plaintext.

This paper proposes a photonic integrated beam forming and steering network (BFN) that uses switched true-time-delay (TTD) silica-based waveguide circuits for phased array antennas. The TTD-BFN has thermooptic switches and variable time delay lines. This TTD-BFN controls four array elements, and can form and steer a beam. An RF test was carried out in the 2.5 GHz microwave frequency range. The experimental results show a peak-to-peak phase error of 6.0 degrees and peak-to-peak amplitude error of 2.0 dB. Array factors obtained from the measured results agree well with the designed ones. This silica-based beam former will be a key element in phased array antennas.

This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.

This paper describes our newly developed intelligent sensor system which comprises two eyes and four ears on a movable head. It can acquire its dynamical visual and auditory image of its surrouding 3-D environment while showing humanlike behavior naturally and autonomously. The most important feature of the sensor system is in an autonomous and optimum sensory architecture of it. This enables the sensor to achieve 1) repid (5 ms) and accurate (2 deg) auditory localization, 2) rapid (0.5 s/65536 pixel) extraction of visual motion in marginal view, 3) rapid (several TV frames' time) eye movement and binocular fixation to a suddenly appeared object, 3) rapid (0.1 s/4096 pixel) extraction of 3-D object profile and image features, which is activated by its own auditory localization and motion detection. We describe in this paper the several key items for realizing this sensor.